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GET /api/patches/122728/?format=api
{ "id": 122728, "url": "http://patches.dpdk.org/api/patches/122728/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230131093346.1261066-8-valex@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230131093346.1261066-8-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230131093346.1261066-8-valex@nvidia.com", "date": "2023-01-31T09:33:36", "name": "[v1,07/16] net/mlx5/hws: add send FW range STE WQE", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "059bd1321f7213169ef47e09ba3190be34b8d09f", "submitter": { "id": 2858, "url": "http://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230131093346.1261066-8-valex@nvidia.com/mbox/", "series": [ { "id": 26709, "url": "http://patches.dpdk.org/api/series/26709/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26709", "date": "2023-01-31T09:33:29", "name": "net/mlx5/hws: support range and partial hash matching", "version": 1, "mbox": "http://patches.dpdk.org/series/26709/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/122728/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/122728/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E2BB041B8D;\n\tTue, 31 Jan 2023 10:35:28 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EB50342D2C;\n\tTue, 31 Jan 2023 10:34:44 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2056.outbound.protection.outlook.com [40.107.243.56])\n by mails.dpdk.org (Postfix) with ESMTP id E172541148\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n \"Matan Azrad\" <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v1 07/16] net/mlx5/hws: add send FW range STE WQE", "Date": "Tue, 31 Jan 2023 11:33:36 +0200", "Message-ID": "<20230131093346.1261066-8-valex@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230131093346.1261066-1-valex@nvidia.com>", "References": "<20230131093346.1261066-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT016:EE_|MW4PR12MB7311:EE_", "X-MS-Office365-Filtering-Correlation-Id": "146e6ada-37ef-4ec9-dc9c-08db036e5f2a", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 3E7Ar5EksJlGrGFt5KwwN+eaf3L2psApmUP0yHKXpk50WUnaWWgn+AzV/T4iaNltiq/8NFRXBo7ZAjXHHEECppL0Uhm2PaFPJ5FuVzbHvKMGgcAhf71+MP8Xtf3Rxu/ditMfDSoOhVuTF7ymcdbnrMjAn8q9hDo8KsY32MCcDxe5/9IB3Zv5adcHqRy7u3p163v82J/wbNwRXG7pRHoSZtIbAiA02DXMSJndlcsOcN6/++5dDKOBP7Yfmr7Jjz94pMi7+ep2Ir2ZBAXWtU74t3VqrhHPAxvQAQRxFZ0wDZXZEcub3xZotm6ce6lh6TAe5ddG4jfbAUqvt6PlBiwF+h3CejhCTfw8sIwrwe4Rd1RAfnMpNDND1uWkNcqMIOu5d2PhqL94pmU49G+q7DZp+js3s1TCSM5izpZjsAkbLY1fHWqFwTKd0/pEKd6w+v6nDQ7kT8DFS/zyQrF3Q0mYz/0xe5NLil465msSxHLYLgtlP0RLFylJ71BRb2pEGvvzwE9R/oKqosMImrvVtFCMKnG+dOV4AO5WDdBonuqqh2GgT4ApGxp1wE7RDLnhCZ/4/ULGmlW5Jz4MtEZneGG/aThC9BvyUJxbBjp3OZV6zYkdq4eBdSTNkQiG320Le0uh2T5feQZHvfhay34tlNGMP6hc/aponHf2APsOiN4o9GlKc7fxGsyDkednzq0yjiihtgwSBjmuOdBDr5AOR+t1nGU+Eow8H93j9SdzluHToHgkmNvsOp1Lni02Fp4X66tt", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(136003)(346002)(376002)(39860400002)(396003)(451199018)(36840700001)(46966006)(40470700004)(7636003)(86362001)(82310400005)(356005)(40460700003)(40480700001)(55016003)(36756003)(426003)(47076005)(336012)(70586007)(70206006)(8676002)(83380400001)(54906003)(6636002)(110136005)(316002)(107886003)(1076003)(16526019)(6286002)(26005)(186003)(7696005)(478600001)(6666004)(2616005)(82740400003)(2906002)(8936002)(41300700001)(36860700001)(4326008)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Jan 2023 09:34:38.0050 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 146e6ada-37ef-4ec9-dc9c-08db036e5f2a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT016.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW4PR12MB7311", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "FW WQE supports complex rules, constructed from 2 STEs,\nfor example:\n Hash(DefinerA)\n SteMatch(DefinerB)\n SteRange(DefinerC)\n DefinerA is a subset of DefinerB\n\nThis complex rule is written using a single FW command which\nhas a single WQE control, STE match data0 and STE range data1.\nFW manages STEs/ICM and coherency between deletion and creation.\nIt is possible to also pass the definer value as part of the\nSTE, this is not supported with current HW.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_send.c | 19 +++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_send.h | 3 +++\n 2 files changed, 22 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_send.c b/drivers/net/mlx5/hws/mlx5dr_send.c\nindex a9958df4f2..51aaf5c8e2 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_send.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_send.c\n@@ -242,11 +242,15 @@ int mlx5dr_send_wqe_fw(struct ibv_context *ibv_ctx,\n \t\t struct mlx5dr_wqe_gta_ctrl_seg *send_wqe_ctrl,\n \t\t void *send_wqe_match_data,\n \t\t void *send_wqe_match_tag,\n+\t\t void *send_wqe_range_data,\n+\t\t void *send_wqe_range_tag,\n \t\t bool is_jumbo,\n \t\t uint8_t gta_opcode)\n {\n+\tbool has_range = send_wqe_range_data || send_wqe_range_tag;\n \tbool has_match = send_wqe_match_data || send_wqe_match_tag;\n \tstruct mlx5dr_wqe_gta_data_seg_ste gta_wqe_data0 = {0};\n+\tstruct mlx5dr_wqe_gta_data_seg_ste gta_wqe_data1 = {0};\n \tstruct mlx5dr_wqe_gta_ctrl_seg gta_wqe_ctrl = {0};\n \tstruct mlx5dr_cmd_generate_wqe_attr attr = {0};\n \tstruct mlx5dr_wqe_ctrl_seg wqe_ctrl = {0};\n@@ -278,6 +282,17 @@ int mlx5dr_send_wqe_fw(struct ibv_context *ibv_ctx,\n \t\tattr.gta_data_0 = (uint8_t *)>a_wqe_data0;\n \t}\n \n+\t/* Set GTA range WQE DATA */\n+\tif (has_range) {\n+\t\tif (send_wqe_range_data)\n+\t\t\tmemcpy(>a_wqe_data1, send_wqe_range_data, sizeof(gta_wqe_data1));\n+\t\telse\n+\t\t\tmlx5dr_send_wqe_set_tag(>a_wqe_data1, send_wqe_range_tag, false);\n+\n+\t\tgta_wqe_data1.rsvd1_definer = htobe32(send_attr->range_definer_id << 8);\n+\t\tattr.gta_data_1 = (uint8_t *)>a_wqe_data1;\n+\t}\n+\n \tattr.pdn = pd_num;\n \tattr.wqe_ctrl = (uint8_t *)&wqe_ctrl;\n \tattr.gta_ctrl = (uint8_t *)>a_wqe_ctrl;\n@@ -336,6 +351,8 @@ void mlx5dr_send_stes_fw(struct mlx5dr_send_engine *queue,\n \t\t\t\t\t ste_attr->wqe_ctrl,\n \t\t\t\t\t ste_attr->wqe_data,\n \t\t\t\t\t ste_attr->wqe_tag,\n+\t\t\t\t\t ste_attr->range_wqe_data,\n+\t\t\t\t\t ste_attr->range_wqe_tag,\n \t\t\t\t\t ste_attr->wqe_tag_is_jumbo,\n \t\t\t\t\t ste_attr->gta_opcode);\n \t\tif (ret)\n@@ -350,6 +367,8 @@ void mlx5dr_send_stes_fw(struct mlx5dr_send_engine *queue,\n \t\t\t\t\t ste_attr->wqe_ctrl,\n \t\t\t\t\t ste_attr->wqe_data,\n \t\t\t\t\t ste_attr->wqe_tag,\n+\t\t\t\t\t ste_attr->range_wqe_data,\n+\t\t\t\t\t ste_attr->range_wqe_tag,\n \t\t\t\t\t ste_attr->wqe_tag_is_jumbo,\n \t\t\t\t\t ste_attr->gta_opcode);\n \t\tif (ret)\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_send.h b/drivers/net/mlx5/hws/mlx5dr_send.h\nindex 1e845b1c7a..47bb66b3c7 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_send.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_send.h\n@@ -161,6 +161,7 @@ struct mlx5dr_send_engine_post_attr {\n \tuint8_t notify_hw;\n \tuint8_t fence;\n \tuint8_t match_definer_id;\n+\tuint8_t range_definer_id;\n \tsize_t len;\n \tstruct mlx5dr_rule *rule;\n \tuint32_t id;\n@@ -182,8 +183,10 @@ struct mlx5dr_send_ste_attr {\n \tuint32_t direct_index;\n \tstruct mlx5dr_send_engine_post_attr send_attr;\n \tstruct mlx5dr_rule_match_tag *wqe_tag;\n+\tstruct mlx5dr_rule_match_tag *range_wqe_tag;\n \tstruct mlx5dr_wqe_gta_ctrl_seg *wqe_ctrl;\n \tstruct mlx5dr_wqe_gta_data_seg_ste *wqe_data;\n+\tstruct mlx5dr_wqe_gta_data_seg_ste *range_wqe_data;\n };\n \n /**\n", "prefixes": [ "v1", "07/16" ] }