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GET /api/patches/121629/?format=api
{ "id": 121629, "url": "http://patches.dpdk.org/api/patches/121629/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230105161020.247780-4-thomas@monjalon.net/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230105161020.247780-4-thomas@monjalon.net>", "list_archive_url": "https://inbox.dpdk.org/dev/20230105161020.247780-4-thomas@monjalon.net", "date": "2023-01-05T16:10:20", "name": "[3/3] net/mlx5: fix Windows build with MinGW GCC 12", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0fffd210c289b9ea85fc95459a5d10f002bcbb5a", "submitter": { "id": 685, "url": "http://patches.dpdk.org/api/people/685/?format=api", "name": "Thomas Monjalon", "email": "thomas@monjalon.net" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230105161020.247780-4-thomas@monjalon.net/mbox/", "series": [ { "id": 26402, "url": "http://patches.dpdk.org/api/series/26402/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26402", "date": "2023-01-05T16:10:17", "name": "fix mlx5 build with MinGW", "version": 1, "mbox": "http://patches.dpdk.org/series/26402/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/121629/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/121629/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D5DFAA00C2;\n\tThu, 5 Jan 2023 17:10:54 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8C28A42D3B;\n\tThu, 5 Jan 2023 17:10:47 +0100 (CET)", "from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com\n [66.111.4.25]) by mails.dpdk.org (Postfix) with ESMTP id 8714B4021E;\n Thu, 5 Jan 2023 17:10:46 +0100 (CET)", "from compute6.internal (compute6.nyi.internal [10.202.2.47])\n by mailout.nyi.internal (Postfix) with ESMTP id 2A7515C0036;\n Thu, 5 Jan 2023 11:10:46 -0500 (EST)", "from mailfrontend1 ([10.202.2.162])\n by compute6.internal (MEProxy); Thu, 05 Jan 2023 11:10:46 -0500", "by mail.messagingengine.com (Postfix) with ESMTPA; Thu,\n 5 Jan 2023 11:10:45 -0500 (EST)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; 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xKmQa386eLKgRl38si7EwPtu/mDNeo=; b=VaVsPdchBycsJ19noHQVKThg5r0Ce\n DKgfHPl7nwzHSX5A90YLMLPyk45cphq3FWvRkGv4cq9gBSp0MD2PeSVZDnFp3BUu\n doqhbKE+nG1NhvsmM0i9lLy2lTuq9EistR5XVk3x0CCudLLcI/Houy0U4qw+seyp\n k8INkK7mALyOJyYC6Ae4PrMIxWnhAZU9a/EAsd7fuKEi965tKaO/8Jis2ZPTP/rg\n mJrFBb1bp51o4k6cHQKzoJIrP5beRpCZvXGZhunBsHDZE5VrTjM/jZYnkqmBCDqT\n KTdOEdDP7O4qcfpFbdxHgZc/F5lv6DaUsiuEVlUbQTieMxNpH76WbBj3Q==" ], "X-ME-Sender": "<xms:hfa2Y9xbrtaXz8riFePPzXkxer74jx5qRCTP0L3S8PMPdGm_bKkRiw>\n <xme:hfa2Y9Tgis2Lvc26a38icYJf5ri9o6vP3EeupCuM1LTmfsPsAFfUEYiLtAO8cBzFd\n aSneh-s_j-dH-cqsQ>", "X-ME-Received": "\n <xmr:hfa2Y3WK8FwJ1GVFZ8dZY--L8rU0OHxbbZbc6-R5lV715ny5ySpaMWz8HyHN1iVYDBzMMZuOY6YbJCDJCLeCLD2T_2j36FY>", "X-ME-Proxy-Cause": "\n gggruggvucftvghtrhhoucdtuddrgedvhedrjeekgdekjecutefuodetggdotefrodftvf\n curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu\n uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc\n fjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefvhhhomhgr\n shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecugg\n ftrfgrthhtvghrnhepvdejhfdugeehvddtieejieegteeuudfgjeeukeeiledthfetveek\n hefhieelhfdtnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh\n homhepthhhohhmrghssehmohhnjhgrlhhonhdrnhgvth", "X-ME-Proxy": "<xmx:hva2Y_h9jw08uBB6rPu8c7xSXqvIahn08Z1_uUUtsT5BWHPmdVcbEQ>\n <xmx:hva2Y_A2KR5Ob_QI5dHtFadB1OWSX1SrDLgkNAlGv91qtwwZ9mQTCg>\n <xmx:hva2Y4KgDiU-YvXdL015nutJIslmx6-MmXdCOmnkP2fubNE1QoJHxw>\n <xmx:hva2Y2PUBbNdiosOCv8RKnyLu7c00PqPMtH_peAvm0agVDB57a5Ecg>", "Feedback-ID": "i47234305:Fastmail", "From": "Thomas Monjalon <thomas@monjalon.net>", "To": "dev@dpdk.org", "Cc": "Tal Shnaiderman <talshn@nvidia.com>, stable@dpdk.org,\n Matan Azrad <matan@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Subject": "[PATCH 3/3] net/mlx5: fix Windows build with MinGW GCC 12", "Date": "Thu, 5 Jan 2023 17:10:20 +0100", "Message-Id": "<20230105161020.247780-4-thomas@monjalon.net>", "X-Mailer": "git-send-email 2.39.0", "In-Reply-To": "<20230105161020.247780-1-thomas@monjalon.net>", "References": "<20230105161020.247780-1-thomas@monjalon.net>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "With recent changes in Meson and MinGW toolchain,\nthe driver mlx5 was not able to compile on Linux for Windows.\n\nThere were errors due to non-typed constants,\nconstant going over int range forbidden in pedantic mode,\nvector Rx functions undefined in Windows case,\nand minimum-comparison of different types.\n\nCc: stable@dpdk.org\n\nSigned-off-by: Thomas Monjalon <thomas@monjalon.net>\n---\n drivers/common/mlx5/meson.build | 4 +-\n drivers/common/mlx5/windows/mlx5_win_defs.h | 100 +++++++++++---------\n drivers/net/mlx5/meson.build | 11 ++-\n drivers/net/mlx5/windows/mlx5_os.c | 4 +-\n 4 files changed, 66 insertions(+), 53 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/meson.build b/drivers/common/mlx5/meson.build\nindex 60ccd95cbc..aea3ae4927 100644\n--- a/drivers/common/mlx5/meson.build\n+++ b/drivers/common/mlx5/meson.build\n@@ -1,9 +1,9 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright 2019 Mellanox Technologies, Ltd\n \n-if not (is_linux or (is_windows and is_ms_linker))\n+if not (is_linux or is_windows)\n build = false\n- reason = 'only supported on Linux and Windows build with clang'\n+ reason = 'only supported on Linux and Windows'\n subdir_done()\n endif\n \ndiff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h\nindex 3554e4a7ff..65da820c5e 100644\n--- a/drivers/common/mlx5/windows/mlx5_win_defs.h\n+++ b/drivers/common/mlx5/windows/mlx5_win_defs.h\n@@ -2,8 +2,10 @@\n * Copyright (C) Mellanox Technologies, Ltd. 2001-2020.\n */\n \n-#ifndef __MLX5_WIN_DEFS_H__\n-#define __MLX5_WIN_DEFS_H__\n+#ifndef MLX5_WIN_DEFS_H\n+#define MLX5_WIN_DEFS_H\n+\n+#include <rte_bitops.h>\n \n enum {\n \tMLX5_CQE_OWNER_MASK\t= 1,\n@@ -40,29 +42,29 @@ enum {\n };\n \n enum mlx5dv_cq_init_attr_mask {\n-\tMLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE\t= 1 << 0,\n-\tMLX5DV_CQ_INIT_ATTR_MASK_FLAGS\t\t= 1 << 1,\n-\tMLX5DV_CQ_INIT_ATTR_MASK_CQE_SIZE = 1 << 2,\n+\tMLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE = RTE_BIT32(0),\n+\tMLX5DV_CQ_INIT_ATTR_MASK_FLAG = RTE_BIT32(1),\n+\tMLX5DV_CQ_INIT_ATTR_MASK_CQE_SIZE = RTE_BIT32(2),\n };\n \n enum mlx5dv_cqe_comp_res_format {\n-\tMLX5DV_CQE_RES_FORMAT_HASH\t\t= 1 << 0,\n-\tMLX5DV_CQE_RES_FORMAT_CSUM\t\t= 1 << 1,\n-\tMLX5DV_CQE_RES_FORMAT_CSUM_STRIDX\t= 1 << 2,\n+\tMLX5DV_CQE_RES_FORMAT_HASH = RTE_BIT32(0),\n+\tMLX5DV_CQE_RES_FORMAT_CSUM = RTE_BIT32(1),\n+\tMLX5DV_CQE_RES_FORMAT_CSUM_STRIDX = RTE_BIT32(2),\n };\n \n enum ibv_access_flags {\n-\tIBV_ACCESS_LOCAL_WRITE\t\t= 1,\n-\tIBV_ACCESS_REMOTE_WRITE\t\t= 1 << 1,\n-\tIBV_ACCESS_REMOTE_READ\t\t= 1 << 2,\n-\tIBV_ACCESS_REMOTE_ATOMIC\t= 1 << 3,\n-\tIBV_ACCESS_MW_BIND\t\t= 1 << 4,\n-\tIBV_ACCESS_ZERO_BASED\t\t= 1 << 5,\n-\tIBV_ACCESS_ON_DEMAND\t\t= 1 << 6,\n+\tIBV_ACCESS_LOCAL_WRITE = RTE_BIT32(0),\n+\tIBV_ACCESS_REMOTE_WRITE = RTE_BIT32(1),\n+\tIBV_ACCESS_REMOTE_READ = RTE_BIT32(2),\n+\tIBV_ACCESS_REMOTE_ATOMIC = RTE_BIT32(3),\n+\tIBV_ACCESS_MW_BIND = RTE_BIT32(4),\n+\tIBV_ACCESS_ZERO_BASED = RTE_BIT32(5),\n+\tIBV_ACCESS_ON_DEMAND = RTE_BIT32(6),\n };\n \n enum mlx5_ib_uapi_devx_create_event_channel_flags {\n-\tMLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = 1 << 0,\n+\tMLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = RTE_BIT32(0),\n };\n \n #define MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA \\\n@@ -85,15 +87,15 @@ enum {\n };\n \n enum {\n-\tMLX5_ETH_WQE_L3_CSUM = (1 << 6),\n-\tMLX5_ETH_WQE_L4_CSUM = (1 << 7),\n+\tMLX5_ETH_WQE_L3_CSUM = RTE_BIT32(6),\n+\tMLX5_ETH_WQE_L4_CSUM = RTE_BIT32(7),\n };\n \n enum {\n-\tMLX5_WQE_CTRL_CQ_UPDATE\t= 2 << 2,\n-\tMLX5_WQE_CTRL_SOLICITED\t= 1 << 1,\n-\tMLX5_WQE_CTRL_FENCE\t= 4 << 5,\n-\tMLX5_WQE_CTRL_INITIATOR_SMALL_FENCE = 1 << 5,\n+\tMLX5_WQE_CTRL_SOLICITED = RTE_BIT32(1),\n+\tMLX5_WQE_CTRL_CQ_UPDATE = RTE_BIT32(3),\n+\tMLX5_WQE_CTRL_INITIATOR_SMALL_FENCE = RTE_BIT32(5),\n+\tMLX5_WQE_CTRL_FENCE = RTE_BIT32(7),\n };\n \n enum {\n@@ -101,6 +103,11 @@ enum {\n \tMLX5_SEND_WQE_SHIFT\t= 6,\n };\n \n+/* Verbs headers do not support -pedantic. */\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+\n /*\n * RX Hash fields enable to set which incoming packet's field should\n * participates in RX Hash. Each flag represent certain packet's field,\n@@ -110,18 +117,22 @@ enum {\n * TCP and UDP flags can't be enabled together on the same QP.\n */\n enum ibv_rx_hash_fields {\n-\tIBV_RX_HASH_SRC_IPV4\t= 1 << 0,\n-\tIBV_RX_HASH_DST_IPV4\t= 1 << 1,\n-\tIBV_RX_HASH_SRC_IPV6\t= 1 << 2,\n-\tIBV_RX_HASH_DST_IPV6\t= 1 << 3,\n-\tIBV_RX_HASH_SRC_PORT_TCP\t= 1 << 4,\n-\tIBV_RX_HASH_DST_PORT_TCP\t= 1 << 5,\n-\tIBV_RX_HASH_SRC_PORT_UDP\t= 1 << 6,\n-\tIBV_RX_HASH_DST_PORT_UDP\t= 1 << 7,\n-\tIBV_RX_HASH_IPSEC_SPI\t\t= 1 << 8,\n-\tIBV_RX_HASH_INNER\t\t= (1 << 31),\n+\tIBV_RX_HASH_SRC_IPV4 = RTE_BIT32(0),\n+\tIBV_RX_HASH_DST_IPV4 = RTE_BIT32(1),\n+\tIBV_RX_HASH_SRC_IPV6 = RTE_BIT32(2),\n+\tIBV_RX_HASH_DST_IPV6 = RTE_BIT32(3),\n+\tIBV_RX_HASH_SRC_PORT_TCP = RTE_BIT32(4),\n+\tIBV_RX_HASH_DST_PORT_TCP = RTE_BIT32(5),\n+\tIBV_RX_HASH_SRC_PORT_UDP = RTE_BIT32(6),\n+\tIBV_RX_HASH_DST_PORT_UDP = RTE_BIT32(7),\n+\tIBV_RX_HASH_IPSEC_SPI = RTE_BIT32(8),\n+\tIBV_RX_HASH_INNER = RTE_BIT32(31),\n };\n \n+#ifdef PEDANTIC\n+#pragma GCC diagnostic error \"-Wpedantic\"\n+#endif\n+\n enum {\n \tMLX5_RCV_DBR\t= 0,\n \tMLX5_SND_DBR\t= 1,\n@@ -141,9 +152,9 @@ enum {\n #endif\n \n enum ibv_flow_flags {\n-\tIBV_FLOW_ATTR_FLAGS_ALLOW_LOOP_BACK = 1 << 0,\n-\tIBV_FLOW_ATTR_FLAGS_DONT_TRAP = 1 << 1,\n-\tIBV_FLOW_ATTR_FLAGS_EGRESS = 1 << 2,\n+\tIBV_FLOW_ATTR_FLAGS_ALLOW_LOOP_BACK = RTE_BIT32(0),\n+\tIBV_FLOW_ATTR_FLAGS_DONT_TRAP = RTE_BIT32(1),\n+\tIBV_FLOW_ATTR_FLAGS_EGRESS = RTE_BIT32(2),\n };\n \n enum ibv_flow_attr_type {\n@@ -240,11 +251,11 @@ struct mlx5_wqe_data_seg {\n \trte_be64_t\t\taddr;\n };\n \n-#define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP\t(1 << 4)\n-#define IBV_DEVICE_RAW_IP_CSUM\t\t\t(1 << 26)\n-#define IBV_RAW_PACKET_CAP_CVLAN_STRIPPING\t(1 << 0)\n-#define IBV_RAW_PACKET_CAP_SCATTER_FCS\t\t(1 << 1)\n-#define IBV_QPT_RAW_PACKET\t\t\t8\n+#define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP RTE_BIT32(4)\n+#define IBV_DEVICE_RAW_IP_CSUM RTE_BIT32(26)\n+#define IBV_RAW_PACKET_CAP_CVLAN_STRIPPING RTE_BIT32(0)\n+#define IBV_RAW_PACKET_CAP_SCATTER_FCS RTE_BIT32(1)\n+#define IBV_QPT_RAW_PACKET 8\n \n enum {\n \tMLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0,\n@@ -254,8 +265,9 @@ enum {\n };\n \n enum {\n-\tMLX5_MATCH_OUTER_HEADERS = 1 << 0,\n-\tMLX5_MATCH_MISC_PARAMETERS = 1 << 1,\n-\tMLX5_MATCH_INNER_HEADERS = 1 << 2,\n+\tMLX5_MATCH_OUTER_HEADERS = RTE_BIT32(0),\n+\tMLX5_MATCH_MISC_PARAMETERS = RTE_BIT32(1),\n+\tMLX5_MATCH_INNER_HEADERS = RTE_BIT32(2),\n };\n-#endif /* __MLX5_WIN_DEFS_H__ */\n+\n+#endif /* MLX5_WIN_DEFS_H */\ndiff --git a/drivers/net/mlx5/meson.build b/drivers/net/mlx5/meson.build\nindex abd507bd88..fe704b1477 100644\n--- a/drivers/net/mlx5/meson.build\n+++ b/drivers/net/mlx5/meson.build\n@@ -49,11 +49,12 @@ if is_linux\n 'mlx5_hws_cnt.c',\n 'mlx5_flow_verbs.c',\n )\n- if (dpdk_conf.has('RTE_ARCH_X86_64')\n- or dpdk_conf.has('RTE_ARCH_ARM64')\n- or dpdk_conf.has('RTE_ARCH_PPC_64'))\n- sources += files('mlx5_rxtx_vec.c')\n- endif\n+endif\n+\n+if (dpdk_conf.has('RTE_ARCH_X86_64')\n+\t or dpdk_conf.has('RTE_ARCH_ARM64')\n+\t or dpdk_conf.has('RTE_ARCH_PPC_64'))\n+\tsources += files('mlx5_rxtx_vec.c')\n endif\n \n cflags_options = [\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex 77f04cc931..7795c0a065 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -193,8 +193,8 @@ mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh)\n \t\t * Once DPDK supports it, take max size from device attr.\n \t\t */\n \t\tsh->dev_cap.ind_table_max_size =\n-\t\t\tRTE_MIN(1 << hca_attr->rss_ind_tbl_cap,\n-\t\t\t\t(unsigned int)RTE_ETH_RSS_RETA_SIZE_512);\n+\t\t\tRTE_MIN((uint32_t) 1 << hca_attr->rss_ind_tbl_cap,\n+\t\t\t\t(uint32_t)RTE_ETH_RSS_RETA_SIZE_512);\n \t\tDRV_LOG(DEBUG, \"Maximum Rx indirection table size is %u\",\n \t\t\tsh->dev_cap.ind_table_max_size);\n \t}\n", "prefixes": [ "3/3" ] }