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GET /api/patches/121317/?format=api
{ "id": 121317, "url": "http://patches.dpdk.org/api/patches/121317/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221223015558.3143279-6-mingxia.liu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221223015558.3143279-6-mingxia.liu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221223015558.3143279-6-mingxia.liu@intel.com", "date": "2022-12-23T01:55:42", "name": "[05/21] net/cpfl: support queue start", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c32c584de789f7eb294ff6751e31d04201302997", "submitter": { "id": 2514, "url": "http://patches.dpdk.org/api/people/2514/?format=api", "name": "Liu, Mingxia", "email": "mingxia.liu@intel.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221223015558.3143279-6-mingxia.liu@intel.com/mbox/", "series": [ { "id": 26253, "url": "http://patches.dpdk.org/api/series/26253/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26253", "date": "2022-12-23T01:55:37", "name": "add support for cpfl PMD in DPDK", "version": 1, "mbox": "http://patches.dpdk.org/series/26253/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/121317/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/121317/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DC3E9A0093;\n\tFri, 23 Dec 2022 03:52:14 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EEEC042D21;\n\tFri, 23 Dec 2022 03:51:57 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id EE85B40685\n for <dev@dpdk.org>; Fri, 23 Dec 2022 03:51:53 +0100 (CET)", "from orsmga006.jf.intel.com ([10.7.209.51])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 22 Dec 2022 18:51:53 -0800", "from dpdk-mingxial-01.sh.intel.com ([10.67.119.112])\n by orsmga006.jf.intel.com with ESMTP; 22 Dec 2022 18:51:51 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1671763914; x=1703299914;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=H/OfNx7XtGdLPywATEAfIep+22Lkbg/Th0T99YnPF1U=;\n b=hYgNtOfgYKzt6tuVrc7Aw2wbI3H4aUSX12FhIiiPQUwk+jszUpLiMwTK\n XyxRywFvQXLceuV47857vR/kVsi9JEsHfMvjUncXPXzdc679M+tZVvl6p\n i0DLGwJaM18Ke4FEQ1DLhDXEVYaMb76CNPy1EtJoZ8vvCuxYXYk/mH0Tk\n HCAzf8Dzgwi9NxUoZy6XOje2L9RCh7ktQGs1KJ6M1jlI9InGhss79XX32\n GBe2phUSf1YrCJmsOaCzCjIaK/YtNPcir1W1yzKKvVnxa5b0ukIaXlQlB\n WY1V21BSg8p+7+ENW7oa20o7jK4O5W6vJMyEmnS9G+fy4aDVbTL0NWn9S g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10569\"; a=\"321467100\"", "E=Sophos;i=\"5.96,267,1665471600\"; d=\"scan'208\";a=\"321467100\"", "E=McAfee;i=\"6500,9779,10569\"; a=\"629707156\"", "E=Sophos;i=\"5.96,267,1665471600\"; d=\"scan'208\";a=\"629707156\"" ], "X-ExtLoop1": "1", "From": "Mingxia Liu <mingxia.liu@intel.com>", "To": "dev@dpdk.org", "Cc": "jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com,\n Mingxia Liu <mingxia.liu@intel.com>", "Subject": "[PATCH 05/21] net/cpfl: support queue start", "Date": "Fri, 23 Dec 2022 01:55:42 +0000", "Message-Id": "<20221223015558.3143279-6-mingxia.liu@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221223015558.3143279-1-mingxia.liu@intel.com>", "References": "<20221223015558.3143279-1-mingxia.liu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for these device ops:\n - rx_queue_start\n - tx_queue_start\n\nSigned-off-by: Mingxia Liu <mingxia.liu@intel.com>\n---\n drivers/net/cpfl/cpfl_ethdev.c | 41 ++++++++++\n drivers/net/cpfl/cpfl_rxtx.c | 138 +++++++++++++++++++++++++++++++++\n drivers/net/cpfl/cpfl_rxtx.h | 4 +\n 3 files changed, 183 insertions(+)", "diff": "diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex 4c259f24e8..d939dcb005 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -184,6 +184,39 @@ cpfl_dev_configure(struct rte_eth_dev *dev)\n \treturn 0;\n }\n \n+static int\n+cpfl_start_queues(struct rte_eth_dev *dev)\n+{\n+\tstruct idpf_rx_queue *rxq;\n+\tstruct idpf_tx_queue *txq;\n+\tint err = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\ttxq = dev->data->tx_queues[i];\n+\t\tif (txq == NULL || txq->tx_deferred_start)\n+\t\t\tcontinue;\n+\t\terr = cpfl_tx_queue_start(dev, i);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to start Tx queue %u\", i);\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\trxq = dev->data->rx_queues[i];\n+\t\tif (rxq == NULL || rxq->rx_deferred_start)\n+\t\t\tcontinue;\n+\t\terr = cpfl_rx_queue_start(dev, i);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to start Rx queue %u\", i);\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\treturn err;\n+}\n+\n static int\n cpfl_dev_start(struct rte_eth_dev *dev)\n {\n@@ -200,6 +233,12 @@ cpfl_dev_start(struct rte_eth_dev *dev)\n \n \tvport->max_pkt_len = dev->data->mtu + CPFL_ETH_OVERHEAD;\n \n+\tret = cpfl_start_queues(dev);\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to start queues\");\n+\t\tgoto err_mtu;\n+\t}\n+\n \tret = idpf_vc_ena_dis_vport(vport, true);\n \tif (ret != 0) {\n \t\tPMD_DRV_LOG(ERR, \"Failed to enable vport\");\n@@ -584,6 +623,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = {\n \t.dev_start\t\t\t= cpfl_dev_start,\n \t.dev_stop\t\t\t= cpfl_dev_stop,\n \t.link_update\t\t\t= cpfl_dev_link_update,\n+\t.rx_queue_start\t\t\t= cpfl_rx_queue_start,\n+\t.tx_queue_start\t\t\t= cpfl_tx_queue_start,\n \t.dev_supported_ptypes_get\t= cpfl_dev_supported_ptypes_get,\n };\n \ndiff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c\nindex 695c79e1db..aa67db1e92 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.c\n+++ b/drivers/net/cpfl/cpfl_rxtx.c\n@@ -474,3 +474,141 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n err_txq_alloc:\n \treturn ret;\n }\n+\n+int\n+cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n+{\n+\tstruct idpf_rx_queue *rxq;\n+\tint err;\n+\n+\tif (rx_queue_id >= dev->data->nb_rx_queues)\n+\t\treturn -EINVAL;\n+\n+\trxq = dev->data->rx_queues[rx_queue_id];\n+\n+\tif (rxq == NULL || !rxq->q_set) {\n+\t\tPMD_DRV_LOG(ERR, \"RX queue %u not available or setup\",\n+\t\t\t\t\trx_queue_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rxq->bufq1 == NULL) {\n+\t\t/* Single queue */\n+\t\terr = idpf_alloc_single_rxq_mbufs(rxq);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX queue mbuf\");\n+\t\t\treturn err;\n+\t\t}\n+\n+\t\trte_wmb();\n+\n+\t\t/* Init the RX tail register. */\n+\t\tIDPF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);\n+\t} else {\n+\t\t/* Split queue */\n+\t\terr = idpf_alloc_split_rxq_mbufs(rxq->bufq1);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX buffer queue mbuf\");\n+\t\t\treturn err;\n+\t\t}\n+\t\terr = idpf_alloc_split_rxq_mbufs(rxq->bufq2);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX buffer queue mbuf\");\n+\t\t\treturn err;\n+\t\t}\n+\n+\t\trte_wmb();\n+\n+\t\t/* Init the RX tail register. */\n+\t\tIDPF_PCI_REG_WRITE(rxq->bufq1->qrx_tail, rxq->bufq1->rx_tail);\n+\t\tIDPF_PCI_REG_WRITE(rxq->bufq2->qrx_tail, rxq->bufq2->rx_tail);\n+\t}\n+\n+\treturn err;\n+}\n+\n+int\n+cpfl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\tstruct idpf_rx_queue *rxq =\n+\t\tdev->data->rx_queues[rx_queue_id];\n+\tint err = 0;\n+\n+\terr = idpf_vc_config_rxq(vport, rxq);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Fail to configure Rx queue %u\", rx_queue_id);\n+\t\treturn err;\n+\t}\n+\n+\terr = cpfl_rx_queue_init(dev, rx_queue_id);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to init RX queue %u\",\n+\t\t\t rx_queue_id);\n+\t\treturn err;\n+\t}\n+\n+\t/* Ready to switch the queue on */\n+\terr = idpf_switch_queue(vport, rx_queue_id, true, true);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to switch RX queue %u on\",\n+\t\t\t rx_queue_id);\n+\t} else {\n+\t\trxq->q_started = true;\n+\t\tdev->data->rx_queue_state[rx_queue_id] =\n+\t\t\tRTE_ETH_QUEUE_STATE_STARTED;\n+\t}\n+\n+\treturn err;\n+}\n+\n+int\n+cpfl_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct idpf_tx_queue *txq;\n+\n+\tif (tx_queue_id >= dev->data->nb_tx_queues)\n+\t\treturn -EINVAL;\n+\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\n+\t/* Init the RX tail register. */\n+\tIDPF_PCI_REG_WRITE(txq->qtx_tail, 0);\n+\n+\treturn 0;\n+}\n+\n+int\n+cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\tstruct idpf_tx_queue *txq =\n+\t\tdev->data->tx_queues[tx_queue_id];\n+\tint err = 0;\n+\n+\terr = idpf_vc_config_txq(vport, txq);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Fail to configure Tx queue %u\", tx_queue_id);\n+\t\treturn err;\n+\t}\n+\n+\terr = cpfl_tx_queue_init(dev, tx_queue_id);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to init TX queue %u\",\n+\t\t\t tx_queue_id);\n+\t\treturn err;\n+\t}\n+\n+\t/* Ready to switch the queue on */\n+\terr = idpf_switch_queue(vport, tx_queue_id, false, true);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to switch TX queue %u on\",\n+\t\t\t tx_queue_id);\n+\t} else {\n+\t\ttxq->q_started = true;\n+\t\tdev->data->tx_queue_state[tx_queue_id] =\n+\t\t\tRTE_ETH_QUEUE_STATE_STARTED;\n+\t}\n+\n+\treturn err;\n+}\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h\nindex fd838d3f07..2fa7950775 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.h\n+++ b/drivers/net/cpfl/cpfl_rxtx.h\n@@ -28,4 +28,8 @@ int cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\t\tuint16_t nb_desc, unsigned int socket_id,\n \t\t\tconst struct rte_eth_rxconf *rx_conf,\n \t\t\tstruct rte_mempool *mp);\n+int cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n+int cpfl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n+int cpfl_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n+int cpfl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n #endif /* _CPFL_RXTX_H_ */\n", "prefixes": [ "05/21" ] }