Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/121113/?format=api
{ "id": 121113, "url": "http://patches.dpdk.org/api/patches/121113/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221220192645.14042-15-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221220192645.14042-15-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221220192645.14042-15-syalavarthi@marvell.com", "date": "2022-12-20T19:26:21", "name": "[v3,14/38] ml/cnxk: add internal structures for tiles and OCM", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "92ac6367adce68cd448af1053b6ab8464c428fd1", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221220192645.14042-15-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26199, "url": "http://patches.dpdk.org/api/series/26199/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=26199", "date": "2022-12-20T19:26:07", "name": "Implementation of ML CNXK driver", "version": 3, "mbox": "http://patches.dpdk.org/series/26199/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/121113/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/121113/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A57EDA0545;\n\tTue, 20 Dec 2022 20:28:31 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D442542D5B;\n\tTue, 20 Dec 2022 20:27:09 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id D816142D15\n for <dev@dpdk.org>; Tue, 20 Dec 2022 20:26:57 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 2BKHShus015480 for <dev@dpdk.org>; Tue, 20 Dec 2022 11:26:57 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mkapj2tpj-7\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 20 Dec 2022 11:26:56 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Tue, 20 Dec 2022 11:26:55 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Tue, 20 Dec 2022 11:26:55 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id DB1D53F706F;\n Tue, 20 Dec 2022 11:26:54 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=A6byNRRUZ1htlA/x1+ylksOLkqv5kjKeqqPay4M9AeE=;\n b=gczt84yTjWG2ldhjXMNE9o+RywAobmYOmdSaIutVK1b1iP9inbFZdYzJlpgxryFKiZSq\n 393TCe4ECJeNLP9nADuymEMsSsniTgcCmCQIX2BZVVurDtT0chY2W55M2Ifsdp6X6lx0\n Jer3YcNaEV7NFcDbi+r3STvMwaS8JSZHOwqATs1UZxC7OZmpiLYjeKwcLB/vELbwwxLa\n vUJcYfTeQWdgkwwst8kh9ZG+MtaGzU/eoBKQKdCOiSgfu43x8ZEWYoHdcj39R6ujNQsT\n ybi4XZ6F0qI3XlttK2QBwXMHUK4uVXVq2EOZEXflBxpMfSanLYtfnrg1EZab1Sk8ghL2 Rw==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v3 14/38] ml/cnxk: add internal structures for tiles and OCM", "Date": "Tue, 20 Dec 2022 11:26:21 -0800", "Message-ID": "<20221220192645.14042-15-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20221220192645.14042-1-syalavarthi@marvell.com>", "References": "<20221208201806.21893-1-syalavarthi@marvell.com>\n <20221220192645.14042-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "l-M-tJz9rkVfd7j_MRrK3ZD9HDVZDBsT", "X-Proofpoint-GUID": "l-M-tJz9rkVfd7j_MRrK3ZD9HDVZDBsT", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-12-20_06,2022-12-20_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added internal structures to handle tile and OCM information and\nOCM to model memory mapping. Initialize the fields to platform\nspecific defaults and compute the OCM / tile requirements for model.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_dev.h | 5 ++\n drivers/ml/cnxk/cn10k_ml_model.c | 53 +++++++++++++++++++++\n drivers/ml/cnxk/cn10k_ml_model.h | 6 +++\n drivers/ml/cnxk/cn10k_ml_ocm.c | 5 ++\n drivers/ml/cnxk/cn10k_ml_ocm.h | 79 ++++++++++++++++++++++++++++++++\n drivers/ml/cnxk/cn10k_ml_ops.c | 29 ++++++++++++\n drivers/ml/cnxk/meson.build | 2 +\n 7 files changed, 179 insertions(+)\n create mode 100644 drivers/ml/cnxk/cn10k_ml_ocm.c\n create mode 100644 drivers/ml/cnxk/cn10k_ml_ocm.h", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h\nindex 7cf6268115..02a4496c97 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.h\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.h\n@@ -7,6 +7,8 @@\n \n #include <roc_api.h>\n \n+#include \"cn10k_ml_ocm.h\"\n+\n /* Marvell OCTEON CN10K ML PMD device name */\n #define MLDEV_NAME_CN10K_PMD ml_cn10k\n \n@@ -215,6 +217,9 @@ struct cn10k_ml_dev {\n \t/* Firmware */\n \tstruct cn10k_ml_fw fw;\n \n+\t/* OCM info */\n+\tstruct cn10k_ml_ocm ocm;\n+\n \t/* Number of models loaded */\n \tuint16_t nb_models_loaded;\n };\ndiff --git a/drivers/ml/cnxk/cn10k_ml_model.c b/drivers/ml/cnxk/cn10k_ml_model.c\nindex 5591e5f572..2281f59591 100644\n--- a/drivers/ml/cnxk/cn10k_ml_model.c\n+++ b/drivers/ml/cnxk/cn10k_ml_model.c\n@@ -8,6 +8,7 @@\n \n #include \"cn10k_ml_dev.h\"\n #include \"cn10k_ml_model.h\"\n+#include \"cn10k_ml_ocm.h\"\n \n static enum rte_ml_io_type\n cn10k_ml_io_type_map(uint8_t type)\n@@ -287,3 +288,55 @@ cn10k_ml_model_addr_update(struct cn10k_ml_model *model, uint8_t *buffer, uint8_\n \t\t\t addr->output[i].sz_d, addr->output[i].sz_q);\n \t}\n }\n+\n+int\n+cn10k_ml_model_ocm_pages_count(struct cn10k_ml_dev *mldev, int16_t model_id, uint8_t *buffer,\n+\t\t\t uint16_t *wb_pages, uint16_t *scratch_pages)\n+{\n+\tstruct cn10k_ml_model_metadata *metadata;\n+\tstruct cn10k_ml_ocm *ocm;\n+\tuint64_t scratch_size;\n+\tuint64_t wb_size;\n+\n+\tmetadata = (struct cn10k_ml_model_metadata *)buffer;\n+\tocm = &mldev->ocm;\n+\n+\t/* Assume wb_size is zero for non-relocatable models */\n+\tif (metadata->model.ocm_relocatable)\n+\t\twb_size = metadata->model.ocm_wb_range_end - metadata->model.ocm_wb_range_start + 1;\n+\telse\n+\t\twb_size = 0;\n+\n+\tif (wb_size % ocm->page_size)\n+\t\t*wb_pages = wb_size / ocm->page_size + 1;\n+\telse\n+\t\t*wb_pages = wb_size / ocm->page_size;\n+\tplt_ml_dbg(\"model_id = %d, wb_size = %\" PRIu64 \", wb_pages = %u\", model_id, wb_size,\n+\t\t *wb_pages);\n+\n+\tscratch_size = ocm->size_per_tile - metadata->model.ocm_tmp_range_floor;\n+\tif (metadata->model.ocm_tmp_range_floor % ocm->page_size)\n+\t\t*scratch_pages = scratch_size / ocm->page_size + 1;\n+\telse\n+\t\t*scratch_pages = scratch_size / ocm->page_size;\n+\tplt_ml_dbg(\"model_id = %d, scratch_size = %\" PRIu64 \", scratch_pages = %u\", model_id,\n+\t\t scratch_size, *scratch_pages);\n+\n+\t/* Check if the model can be loaded on OCM */\n+\tif ((*wb_pages + *scratch_pages) > ML_CN10K_OCM_NUMPAGES) {\n+\t\tplt_err(\"Cannot create the model, OCM relocatable = %u\",\n+\t\t\tmetadata->model.ocm_relocatable);\n+\t\tplt_err(\"wb_pages (%u) + scratch_pages (%u) > %u\", *wb_pages, *scratch_pages,\n+\t\t\tML_CN10K_OCM_NUMPAGES);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* Update scratch_pages to block the full tile for OCM non-relocatable model. This would\n+\t * prevent the library from allocating the remaining space on the tile to other models.\n+\t */\n+\tif (!metadata->model.ocm_relocatable)\n+\t\t*scratch_pages =\n+\t\t\tPLT_MAX(PLT_U64_CAST(*scratch_pages), PLT_U64_CAST(ML_CN10K_OCM_NUMPAGES));\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/ml/cnxk/cn10k_ml_model.h b/drivers/ml/cnxk/cn10k_ml_model.h\nindex 1f329323a6..80653f18a9 100644\n--- a/drivers/ml/cnxk/cn10k_ml_model.h\n+++ b/drivers/ml/cnxk/cn10k_ml_model.h\n@@ -10,6 +10,7 @@\n #include <roc_api.h>\n \n #include \"cn10k_ml_dev.h\"\n+#include \"cn10k_ml_ocm.h\"\n \n /* Maximum number of models per device */\n #define ML_CN10K_MAX_MODELS 16\n@@ -420,6 +421,9 @@ struct cn10k_ml_model {\n \t/* Address structure */\n \tstruct cn10k_ml_model_addr addr;\n \n+\t/* Tile and memory information object */\n+\tstruct cn10k_ml_ocm_model_map model_mem_map;\n+\n \t/* Spinlock, used to update model state */\n \tplt_spinlock_t lock;\n \n@@ -431,5 +435,7 @@ int cn10k_ml_model_metadata_check(uint8_t *buffer, uint64_t size);\n void cn10k_ml_model_metadata_update(struct cn10k_ml_model_metadata *metadata);\n void cn10k_ml_model_addr_update(struct cn10k_ml_model *model, uint8_t *buffer,\n \t\t\t\tuint8_t *base_dma_addr);\n+int cn10k_ml_model_ocm_pages_count(struct cn10k_ml_dev *mldev, int16_t model_id, uint8_t *buffer,\n+\t\t\t\t uint16_t *wb_pages, uint16_t *scratch_pages);\n \n #endif /* _CN10K_ML_MODEL_H_ */\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ocm.c b/drivers/ml/cnxk/cn10k_ml_ocm.c\nnew file mode 100644\nindex 0000000000..b1c62f2963\n--- /dev/null\n+++ b/drivers/ml/cnxk/cn10k_ml_ocm.c\n@@ -0,0 +1,5 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 Marvell.\n+ */\n+\n+#include \"cn10k_ml_ocm.h\"\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ocm.h b/drivers/ml/cnxk/cn10k_ml_ocm.h\nnew file mode 100644\nindex 0000000000..44390396f9\n--- /dev/null\n+++ b/drivers/ml/cnxk/cn10k_ml_ocm.h\n@@ -0,0 +1,79 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 Marvell.\n+ */\n+\n+#ifndef _CN10K_ML_OCM_H_\n+#define _CN10K_ML_OCM_H_\n+\n+#include <rte_mldev.h>\n+\n+/* Page size in bytes. */\n+#define ML_CN10K_OCM_PAGESIZE 0x4000\n+\n+/* Number of OCM tiles. */\n+#define ML_CN10K_OCM_NUMTILES 0x8\n+\n+/* OCM in bytes, per tile. */\n+#define ML_CN10K_OCM_TILESIZE 0x100000\n+\n+/* OCM pages, per tile. */\n+#define ML_CN10K_OCM_NUMPAGES (ML_CN10K_OCM_TILESIZE / ML_CN10K_OCM_PAGESIZE)\n+\n+/* Maximum OCM mask words, per tile, 8 bit words. */\n+#define ML_CN10K_OCM_MASKWORDS (ML_CN10K_OCM_NUMPAGES / 8)\n+\n+/* OCM and Tile information structure */\n+struct cn10k_ml_ocm_tile_info {\n+\t/* Mask of used / allotted pages on tile's OCM */\n+\tuint8_t ocm_mask[ML_CN10K_OCM_MASKWORDS];\n+\n+\t/* Last pages in the tile's OCM used for weights and bias, default = -1 */\n+\tint last_wb_page;\n+\n+\t/* Number pages used for scratch memory on the tile's OCM */\n+\tuint16_t scratch_pages;\n+};\n+\n+/* Model OCM map structure */\n+struct cn10k_ml_ocm_model_map {\n+\t/* Status of OCM reservation */\n+\tbool ocm_reserved;\n+\n+\t/* Mask of OCM tiles for the model */\n+\tuint64_t tilemask;\n+\n+\t/* Start page for the model load, default = -1 */\n+\tint wb_page_start;\n+\n+\t/* Number of pages required for weights and bias */\n+\tuint16_t wb_pages;\n+\n+\t/* Number of pages required for scratch memory */\n+\tuint16_t scratch_pages;\n+};\n+\n+/* OCM state structure */\n+struct cn10k_ml_ocm {\n+\t/* OCM spinlock, used to update OCM state */\n+\trte_spinlock_t lock;\n+\n+\t/* Number of OCM tiles */\n+\tuint8_t num_tiles;\n+\n+\t/* OCM size per each tile */\n+\tuint64_t size_per_tile;\n+\n+\t/* Size of OCM page */\n+\tuint64_t page_size;\n+\n+\t/* Number of OCM pages */\n+\tuint16_t num_pages;\n+\n+\t/* Words per OCM mask */\n+\tuint16_t mask_words;\n+\n+\t/* OCM memory info and status*/\n+\tstruct cn10k_ml_ocm_tile_info tile_ocm_info[ML_CN10K_OCM_NUMTILES];\n+};\n+\n+#endif /* _CN10K_ML_OCM_H_ */\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex 20f15ec35d..9ccf52332f 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -126,8 +126,10 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \tstruct rte_ml_dev_info dev_info;\n \tstruct cn10k_ml_model *model;\n \tstruct cn10k_ml_dev *mldev;\n+\tstruct cn10k_ml_ocm *ocm;\n \tstruct cn10k_ml_qp *qp;\n \tuint32_t mz_size;\n+\tuint16_t tile_id;\n \tint16_t model_id;\n \tuint16_t qp_id;\n \tint ret;\n@@ -250,6 +252,18 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \t}\n \tdev->data->nb_models = conf->nb_models;\n \n+\tocm = &mldev->ocm;\n+\tocm->num_tiles = ML_CN10K_OCM_NUMTILES;\n+\tocm->size_per_tile = ML_CN10K_OCM_TILESIZE;\n+\tocm->page_size = ML_CN10K_OCM_PAGESIZE;\n+\tocm->num_pages = ocm->size_per_tile / ocm->page_size;\n+\tocm->mask_words = ocm->num_pages / (8 * sizeof(uint8_t));\n+\n+\tfor (tile_id = 0; tile_id < ocm->num_tiles; tile_id++)\n+\t\tocm->tile_ocm_info[tile_id].last_wb_page = -1;\n+\n+\trte_spinlock_init(&ocm->lock);\n+\n \tmldev->nb_models_loaded = 0;\n \tmldev->state = ML_CN10K_DEV_STATE_CONFIGURED;\n \n@@ -416,6 +430,8 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n \tconst struct plt_memzone *mz;\n \tsize_t model_data_size;\n \tuint8_t *base_dma_addr;\n+\tuint16_t scratch_pages;\n+\tuint16_t wb_pages;\n \tuint64_t mz_size;\n \tuint16_t idx;\n \tbool found;\n@@ -441,6 +457,11 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n \t\treturn -ENOMEM;\n \t}\n \n+\t/* Get WB and scratch pages, check if model can be loaded. */\n+\tret = cn10k_ml_model_ocm_pages_count(mldev, idx, params->addr, &wb_pages, &scratch_pages);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n \t/* Compute memzone size */\n \tmetadata = (struct cn10k_ml_model_metadata *)params->addr;\n \tmodel_data_size = metadata->init_model.file_size + metadata->main_model.file_size +\n@@ -478,6 +499,14 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n \t/* Copy data from load to run. run address to be used by MLIP */\n \trte_memcpy(model->addr.base_dma_addr_run, model->addr.base_dma_addr_load, model_data_size);\n \n+\t/* Initialize model_mem_map */\n+\tmemset(&model->model_mem_map, 0, sizeof(struct cn10k_ml_ocm_model_map));\n+\tmodel->model_mem_map.ocm_reserved = false;\n+\tmodel->model_mem_map.tilemask = 0;\n+\tmodel->model_mem_map.wb_page_start = -1;\n+\tmodel->model_mem_map.wb_pages = wb_pages;\n+\tmodel->model_mem_map.scratch_pages = scratch_pages;\n+\n \tplt_spinlock_init(&model->lock);\n \tmodel->state = ML_CN10K_MODEL_STATE_LOADED;\n \tdev->data->models[idx] = model;\ndiff --git a/drivers/ml/cnxk/meson.build b/drivers/ml/cnxk/meson.build\nindex 84ff622784..2f220a26b5 100644\n--- a/drivers/ml/cnxk/meson.build\n+++ b/drivers/ml/cnxk/meson.build\n@@ -11,12 +11,14 @@ driver_sdk_headers = files(\n 'cn10k_ml_dev.h',\n 'cn10k_ml_ops.h',\n 'cn10k_ml_model.h',\n+ 'cn10k_ml_ocm.h',\n )\n \n sources = files(\n 'cn10k_ml_dev.c',\n 'cn10k_ml_ops.c',\n 'cn10k_ml_model.c',\n+ 'cn10k_ml_ocm.c',\n )\n \n deps += ['mldev', 'common_ml', 'common_cnxk', 'kvargs', 'hash']\n", "prefixes": [ "v3", "14/38" ] }