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GET /api/patches/120025/?format=api
{ "id": 120025, "url": "http://patches.dpdk.org/api/patches/120025/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221122051308.194-2-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221122051308.194-2-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221122051308.194-2-getelson@nvidia.com", "date": "2022-11-22T05:13:07", "name": "[v2,2/2] doc: update MLX5 LRO limitation", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "4f734f27c383389d170f4572b35cd248c0f4cebc", "submitter": { "id": 1882, "url": "http://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221122051308.194-2-getelson@nvidia.com/mbox/", "series": [ { "id": 25844, "url": "http://patches.dpdk.org/api/series/25844/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25844", "date": "2022-11-22T05:13:06", "name": "[v2,1/2] net/mlx5: fix port private max LRO msg size", "version": 2, "mbox": "http://patches.dpdk.org/series/25844/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/120025/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/120025/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 819DBA0577;\n\tTue, 22 Nov 2022 06:13:46 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 73F9542D3F;\n\tTue, 22 Nov 2022 06:13:46 +0100 (CET)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2079.outbound.protection.outlook.com [40.107.244.79])\n by mails.dpdk.org (Postfix) with ESMTP id 9E6AA40A80;\n Tue, 22 Nov 2022 06:13:44 +0100 (CET)", "from DM6PR12CA0032.namprd12.prod.outlook.com (2603:10b6:5:1c0::45)\n by IA1PR12MB6434.namprd12.prod.outlook.com (2603:10b6:208:3ae::10) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.15; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <matan@nvidia.com>, <rasland@nvidia.com>,\n <stable@dpdk.org>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Subject": "[PATCH v2 2/2] doc: update MLX5 LRO limitation", "Date": "Tue, 22 Nov 2022 07:13:07 +0200", "Message-ID": "<20221122051308.194-2-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20221122051308.194-1-getelson@nvidia.com>", "References": "<20221117143901.27957-1-getelson@nvidia.com>\n <20221122051308.194-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT087:EE_|IA1PR12MB6434:EE_", "X-MS-Office365-Filtering-Correlation-Id": "543ec8cd-d617-462f-1df5-08dacc485273", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n LGQUzokI4i9azcIFTtOYUFllT34UKkxttoqUb9O7SGmdp07379WlZHucOOXtr0YhiAfmAOfO0OAoSrlKXLP1R6TKwRiEzd5k9BlI/sxE+ZGsn6+7d2i8ZdqXkGdyVqT/7NA2k53NA0DaKMWBWyrCtVzXkH8Q051j8oeSE2r5yf9QPHHZ1px4olzemDLDWkYkHG9REVj1FLHf6msT5+nhuJQWJDZmWctE9HXIPO6Ew6PobHLD6n81H/rRhj/AHQzWo3mjlt2l28C5YRaD+opxbJ8YZ9YB/aeTs/sfDv8Zb2BAh8EAeNcmyu3ObHGhGYt5SRZvjAsIUJJyWzVRt1lSkIjYqC4oP1RY0MW4zQVZ/WflClzaTutram8KYRtRu2HixHkQMpL1YylL+GkvnHbeNgAYckrKz+RzMslmDdfkjKIzOwFx1c8iD/XKW1KiUa6sPU1G4XkWOTBmOS6GxCS6Vo+APqy5Tu7XWbu0LC25v4yHDCSR8RZgjBKAw2etIRedNWPbQJ8Vd6nWbGqKaUsL3DD0Y+Lf58cNJTGd1deDwRfsKlBA7et+8UzeR012x17RvNeUaFcpvQ1hLnrxA9geFXigD0GIkoI4u1zYdaE7oLhKd97sqVLJTdJvzLCmc/g2E6Iw8Qa9HKJKQen2DvNliMROh8a7KlOV+UIRzhwVQWUkPrum980LoDjlOrXnQqPHxmAqoRMWLBSI35Gltkds8w==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(39860400002)(396003)(136003)(346002)(376002)(451199015)(36840700001)(46966006)(40470700004)(36756003)(70586007)(70206006)(450100002)(15650500001)(2906002)(6286002)(26005)(16526019)(1076003)(7696005)(336012)(4326008)(478600001)(40480700001)(54906003)(316002)(55016003)(6916009)(2616005)(40460700003)(36860700001)(86362001)(82310400005)(8676002)(186003)(41300700001)(83380400001)(356005)(7636003)(426003)(4744005)(82740400003)(5660300002)(107886003)(47076005)(8936002)(6666004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 Nov 2022 05:13:41.7771 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 543ec8cd-d617-462f-1df5-08dacc485273", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT087.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB6434", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Maximal LRO message size must be multiply of 256.\nOtherwise, TCP payload may not fit into a single WQE.\n\nCc: stable@dpdk.org\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\nv2: move the patch to LRO section.\n---\n doc/guides/nics/mlx5.rst | 2 ++\n 1 file changed, 2 insertions(+)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 4f0db21dde..e77d79774b 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -411,6 +411,8 @@ Limitations\n - LRO packet aggregation is performed by HW only for packet size larger than\n ``lro_min_mss_size``. This value is reported on device start, when debug\n mode is enabled.\n+ - The driver rounds down the ``max_lro_pkt_size`` value in the port configuration\n+ to a multiple of 256 due to HW limitation.\n \n - CRC:\n \n", "prefixes": [ "v2", "2/2" ] }