Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 119296,
    "url": "http://patches.dpdk.org/api/patches/119296/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221030161200.32662-1-valex@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20221030161200.32662-1-valex@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20221030161200.32662-1-valex@nvidia.com",
    "date": "2022-10-30T16:11:59",
    "name": "net/mlx5/hws: remove deprecated rte_atomic",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "dd95776acf6aeb8e508aa209a8e3151b457a780d",
    "submitter": {
        "id": 2858,
        "url": "http://patches.dpdk.org/api/people/2858/?format=api",
        "name": "Alex Vesker",
        "email": "valex@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221030161200.32662-1-valex@nvidia.com/mbox/",
    "series": [
        {
            "id": 25485,
            "url": "http://patches.dpdk.org/api/series/25485/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25485",
            "date": "2022-10-30T16:11:59",
            "name": "net/mlx5/hws: remove deprecated rte_atomic",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/25485/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/119296/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/119296/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2556BA00C2;\n\tSun, 30 Oct 2022 17:12:25 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CDDCF40693;\n\tSun, 30 Oct 2022 17:12:24 +0100 (CET)",
            "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2061.outbound.protection.outlook.com [40.107.223.61])\n by mails.dpdk.org (Postfix) with ESMTP id 38A5B40151\n for <dev@dpdk.org>; Sun, 30 Oct 2022 17:12:23 +0100 (CET)",
            "from BN9PR03CA0305.namprd03.prod.outlook.com (2603:10b6:408:112::10)\n by BL1PR12MB5032.namprd12.prod.outlook.com (2603:10b6:208:30a::12)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.19; Sun, 30 Oct\n 2022 16:12:21 +0000",
            "from BN8NAM11FT084.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:112:cafe::f1) by BN9PR03CA0305.outlook.office365.com\n (2603:10b6:408:112::10) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.16 via Frontend\n Transport; Sun, 30 Oct 2022 16:12:21 +0000",
            "from mail.nvidia.com (216.228.117.161) by\n BN8NAM11FT084.mail.protection.outlook.com (10.13.176.169) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.5769.14 via Frontend Transport; Sun, 30 Oct 2022 16:12:20 +0000",
            "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Sun, 30 Oct\n 2022 09:12:18 -0700",
            "from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Sun, 30 Oct\n 2022 09:12:15 -0700"
        ],
        "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=HBOaPSCqu5OTNqOyeGKAv9kf87M3h+iiS6dgR/a9eLriCgOC13TFfOqwISpMfZMiYdJ0vRGZh8j0yxxo4Bhw2kZkSq+zGWoAITOtBhpmfD6248TzXImWgZiCFJWStO8EyHFlgF1kj5sNnU70IbnnQg56Ykkdi0WrdlUtU2vdbiOMMfEM3QrSWSQwQFI/W5r9JgWlACy/FpiwhIfX5RlHifSDMUw840BxRSXhqgQOmysce47CvX+2uhwJ1yIQjTTa8Iheq7oYTpc6YSEhwq4aLApSlTmvt65AIRAt0keu8FOIhyxNV9XZLNzORz/FKyDYntfY2NtjZX346E8LN04H2w==",
        "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=3f8byhd2YNL85MK6H0FwDys3nfEG9bemN7uX17gHvzY=;\n b=eXznfXAVI/8RbyZBJp391Z5xyNJEME/tnWizEdX+oWdogjnpRT7OeeHYYCUhgOrtPHmszKG9wLIknelaLamSOdkydt4P5NqSKga/gD9KWsdKeJIRm7xgXgquVBl5HiEQ5KZ9ylEFAjkT8S5XVTZrNEDlAe9fH8GPXqhleD4IOR0rlKb1+HIP3ybzEdBS3BbKkvpSJmSmsTyCuRQteFDCtUW7O02DhF/sDICWrIOWW/MR+Zjq/iSu7aVDHs4DlwqChaB1iGI4nEKCyzI+WtF/3zN0uKNhVhkF4GMG5vfj13n2xtzCDTJG/M9VaPGdZ75h+Z9UEba/eSjk7pOInegNuw==",
        "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=3f8byhd2YNL85MK6H0FwDys3nfEG9bemN7uX17gHvzY=;\n b=RMgAm60pqhnOU49J/1dRthYu4+mh1irQuX10epa6kwiYt0eKbOZSXKMCMfBCTvAgeiTsJbL4A9u+UKkOlb5Sdtd/rXXbB+k6eC7j4LHTtAwIID8oFi8s7j8Py7uuOhGgSGFqEkiVuhekgdl7Y53hU8pwvXpQpmzBnXypwYlveQNbkNc50dPeGuicg7zhGMF8HK8FmSV41qL6vWaP+61nxGWrhRoJF+HGCrQA3tX3Rh3l2XVmvuJG5owA9aEh+1YnSL2dcz7JwvV3joFsxsICxVUesYZXrf0lXNbDQQQ83Po+51esj5baOfxR26EeVnpYpcYGlCt1Jmcuj0urOAe79w==",
        "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;",
        "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C",
        "From": "Alex Vesker <valex@nvidia.com>",
        "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>",
        "CC": "<dev@dpdk.org>, <orika@nvidia.com>",
        "Subject": "[PATCH] net/mlx5/hws: remove deprecated rte_atomic",
        "Date": "Sun, 30 Oct 2022 18:11:59 +0200",
        "Message-ID": "<20221030161200.32662-1-valex@nvidia.com>",
        "X-Mailer": "git-send-email 2.18.1",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.126.231.35]",
        "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)",
        "X-EOPAttributedMessage": "0",
        "X-MS-PublicTrafficType": "Email",
        "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT084:EE_|BL1PR12MB5032:EE_",
        "X-MS-Office365-Filtering-Correlation-Id": "fbf05a0a-74e3-4633-4292-08daba91861e",
        "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr",
        "X-MS-Exchange-SenderADCheck": "1",
        "X-MS-Exchange-AntiSpam-Relay": "0",
        "X-Microsoft-Antispam": "BCL:0;",
        "X-Microsoft-Antispam-Message-Info": "\n yFL4Po16UFEAcAns3fqAhcYk2tjCA2jHJzc5TzTq/RGj5KCxufbFDI61++kZT6HCix5CUC21w9GFY+xHebkNAZ8N28V3s9xAYjeg40NNhedPt0H4/Rw4p/CS+VgloXPF2Y0h3M8fomZJiOgBEegaQ0Uhh98g1OtsltW8HrzakaXowamHZY4ItWwDMgiP8jXTq/ijK4h5lrlCBXyvVQH6qWkgJdVCl7IQpgoAWg6yD6iBumBH31Xxy58SRPAnAJD2gvAZDYeieUny188CZxyEJuwzFYc/WE06/CjOdKgFSocmoh+Ujnn7zWxbcG5r2T/nX0ZXJgkmyPEl92LIcyP6tZ5KOqxVpwyEvcEeiBFa/QIcGnwfotWDdEaajBFwYRfSt+O3s953caXk2Gt3ZQTNhrIvKV8Ta6yieuUxpWcm60HS5eAtC1Y1dKFtDa+kXkv8pGf5MgQPt/JyvGDtbKQ92j3ICLB/1nYwbNfFU+XyqG5lK6eXAfcTBLyBADNUgttt9N9w4NsQRY9+rugUu5LnfyH+87xrYQTmPXtfKTGE42ocjErMYi7U8wG4T1k5BmhQJteZTsI1nn9gkUdBjg536ZMSO+ztC17cj4VDGqf593yY0gXAFGPsevUFfaEeg4iDFRpqKH3Dt+0Evs9hD0ssyvB2BCWUSSV8pTjysQNk/QlgHpAMfAIy5pVzo6cBp5rHZAB486nZl+ERF0ZgRlBxv/BQLMJt57AG4jNgVFMtzUlfdx4FLmIhBTA4034XdS/kNhvtwM1eMVutzYufCkI/mg==",
        "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(136003)(396003)(376002)(346002)(39860400002)(451199015)(36840700001)(46966006)(40470700004)(478600001)(82310400005)(82740400003)(110136005)(356005)(7636003)(6636002)(54906003)(316002)(2616005)(40460700003)(36756003)(83380400001)(8936002)(16526019)(86362001)(6666004)(107886003)(336012)(2906002)(1076003)(186003)(7696005)(5660300002)(36860700001)(55016003)(4326008)(426003)(47076005)(70586007)(70206006)(40480700001)(8676002)(26005)(6286002)(41300700001);\n DIR:OUT; SFP:1101;",
        "X-OriginatorOrg": "Nvidia.com",
        "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Oct 2022 16:12:20.7313 (UTC)",
        "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n fbf05a0a-74e3-4633-4292-08daba91861e",
        "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a",
        "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]",
        "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT084.eop-nam11.prod.protection.outlook.com",
        "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous",
        "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5032",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "The use of rte_atomic functions is deprecated and is not\nrequired in HWS code. HWS refcounts are used only during\ncontrol and always under lock.\n\nFixes: f8c8a6d8440d (\"net/mlx5/hws: add action object\")\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_action.c  | 8 +++-----\n drivers/net/mlx5/hws/mlx5dr_action.h  | 2 +-\n drivers/net/mlx5/hws/mlx5dr_pat_arg.c | 8 +++-----\n drivers/net/mlx5/hws/mlx5dr_pat_arg.h | 2 +-\n 4 files changed, 8 insertions(+), 12 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c\nindex 755d5d09cf..a9e12aa1f5 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_action.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_action.c\n@@ -83,7 +83,7 @@ static int mlx5dr_action_get_shared_stc_nic(struct mlx5dr_context *ctx,\n \n \tpthread_spin_lock(&ctx->ctrl_lock);\n \tif (ctx->common_res[tbl_type].shared_stc[stc_type]) {\n-\t\trte_atomic32_add(&ctx->common_res[tbl_type].shared_stc[stc_type]->refcount, 1);\n+\t\tctx->common_res[tbl_type].shared_stc[stc_type]->refcount++;\n \t\tpthread_spin_unlock(&ctx->ctrl_lock);\n \t\treturn 0;\n \t}\n@@ -123,9 +123,7 @@ static int mlx5dr_action_get_shared_stc_nic(struct mlx5dr_context *ctx,\n \t}\n \n \tctx->common_res[tbl_type].shared_stc[stc_type] = shared_stc;\n-\n-\trte_atomic32_init(&ctx->common_res[tbl_type].shared_stc[stc_type]->refcount);\n-\trte_atomic32_set(&ctx->common_res[tbl_type].shared_stc[stc_type]->refcount, 1);\n+\tctx->common_res[tbl_type].shared_stc[stc_type]->refcount = 1;\n \n \tpthread_spin_unlock(&ctx->ctrl_lock);\n \n@@ -145,7 +143,7 @@ static void mlx5dr_action_put_shared_stc_nic(struct mlx5dr_context *ctx,\n \tstruct mlx5dr_action_shared_stc *shared_stc;\n \n \tpthread_spin_lock(&ctx->ctrl_lock);\n-\tif (!rte_atomic32_dec_and_test(&ctx->common_res[tbl_type].shared_stc[stc_type]->refcount)) {\n+\tif (--ctx->common_res[tbl_type].shared_stc[stc_type]->refcount) {\n \t\tpthread_spin_unlock(&ctx->ctrl_lock);\n \t\treturn;\n \t}\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_action.h b/drivers/net/mlx5/hws/mlx5dr_action.h\nindex f14d91f994..3b31ffc90e 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_action.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_action.h\n@@ -70,7 +70,7 @@ struct mlx5dr_action_default_stc {\n \n struct mlx5dr_action_shared_stc {\n \tstruct mlx5dr_pool_chunk remove_header;\n-\trte_atomic32_t refcount;\n+\tuint32_t refcount;\n };\n \n struct mlx5dr_actions_apply_data {\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_pat_arg.c b/drivers/net/mlx5/hws/mlx5dr_pat_arg.c\nindex 46fdc8ce68..df451f1ae0 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_pat_arg.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_pat_arg.c\n@@ -128,7 +128,7 @@ mlx5dr_pat_get_existing_cached_pattern(struct mlx5dr_pattern_cache *cache,\n \t\t/* LRU: move it to be first in the list */\n \t\tLIST_REMOVE(cached_pattern, next);\n \t\tLIST_INSERT_HEAD(&cache->head, cached_pattern, next);\n-\t\trte_atomic32_add(&cached_pattern->refcount, 1);\n+\t\tcached_pattern->refcount++;\n \t}\n \n \treturn cached_pattern;\n@@ -179,9 +179,7 @@ mlx5dr_pat_add_pattern_to_cache(struct mlx5dr_pattern_cache *cache,\n \t       num_of_actions * MLX5DR_MODIFY_ACTION_SIZE);\n \n \tLIST_INSERT_HEAD(&cache->head, cached_pattern, next);\n-\n-\trte_atomic32_init(&cached_pattern->refcount);\n-\trte_atomic32_set(&cached_pattern->refcount, 1);\n+\tcached_pattern->refcount = 1;\n \n \treturn cached_pattern;\n \n@@ -212,7 +210,7 @@ mlx5dr_pat_put_pattern(struct mlx5dr_pattern_cache *cache,\n \t\tgoto out;\n \t}\n \n-\tif (!rte_atomic32_dec_and_test(&cached_pattern->refcount))\n+\tif (--cached_pattern->refcount)\n \t\tgoto out;\n \n \tmlx5dr_pat_remove_pattern(cached_pattern);\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_pat_arg.h b/drivers/net/mlx5/hws/mlx5dr_pat_arg.h\nindex 8a4670427f..d9353e9a3e 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_pat_arg.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_pat_arg.h\n@@ -35,7 +35,7 @@ struct mlx5dr_pat_cached_pattern {\n \t\tuint8_t *data;\n \t\tuint16_t num_of_actions;\n \t} mh_data;\n-\trte_atomic32_t refcount;\n+\tuint32_t refcount;\n \tLIST_ENTRY(mlx5dr_pat_cached_pattern) next;\n };\n \n",
    "prefixes": []
}