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GET /api/patches/119033/?format=api
{ "id": 119033, "url": "http://patches.dpdk.org/api/patches/119033/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221013181602.873166-2-mpiszczek@ddn.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221013181602.873166-2-mpiszczek@ddn.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221013181602.873166-2-mpiszczek@ddn.com", "date": "2022-10-13T18:16:02", "name": "[v5] pci: read amd iommu virtual address width", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "90709e6811716a16ae15b5d2f9ac7380a49117eb", "submitter": { "id": 2840, "url": "http://patches.dpdk.org/api/people/2840/?format=api", "name": "Michael Piszczek", "email": "mpiszczek@ddn.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221013181602.873166-2-mpiszczek@ddn.com/mbox/", "series": [ { "id": 25390, "url": "http://patches.dpdk.org/api/series/25390/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25390", "date": "2022-10-13T18:16:02", "name": "[v5] pci: read amd iommu virtual address width", "version": 5, "mbox": "http://patches.dpdk.org/series/25390/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/119033/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/119033/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=cte94XJ/7LixxMoVF2a+B3L9lQTpMm9utltXXd76JwWC0hGNAqyN8iIKorMoQ052k1Nhl2TKjLvvRsR1635nlvsiAVvPISysq5nfqTHHoMc+IUVQf7YeP8jx5IyXBxdmg66mPtnrA9BHn1oKpsW50H2v9y+/zPzyD4ZmwEupdog=", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 50.222.100.11)\n smtp.mailfrom=ddn.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=ddn.com;", "Received-SPF": "Pass (protection.outlook.com: domain of ddn.com designates\n 50.222.100.11 as permitted sender) receiver=protection.outlook.com;\n client-ip=50.222.100.11; helo=uww-mx01.datadirectnet.com; pr=C", "From": "Michael Piszczek <mpiszczek@ddn.com>", "To": "dev@dpdk.org", "Cc": "Vipin.Varghese@amd.com,\n\tMichael Piszczek <mpiszczek@ddn.com>", "Subject": "[PATCH v5] pci: read amd iommu virtual address width", "Date": "Thu, 13 Oct 2022 20:16:02 +0200", "Message-Id": "<20221013181602.873166-2-mpiszczek@ddn.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20221013181602.873166-1-mpiszczek@ddn.com>", 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SFS:(13230022)(4636009)(136003)(376002)(396003)(39850400004)(346002)(451199015)(46966006)(36840700001)(70586007)(356005)(6916009)(186003)(83380400001)(26005)(47076005)(82740400003)(1076003)(336012)(6266002)(2906002)(36860700001)(82310400005)(8936002)(81166007)(70206006)(478600001)(8676002)(2616005)(5660300002)(6666004)(41300700001)(4326008)(40480700001)(86362001)(316002)(36756003)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "ddn.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 Oct 2022 18:16:07.5869 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8d6a927c-d162-4760-49d5-08daad46ffc3", "X-MS-Exchange-CrossTenant-Id": "753b6e26-6fd3-43e6-8248-3f1735d59bb4", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=753b6e26-6fd3-43e6-8248-3f1735d59bb4; Ip=[50.222.100.11];\n Helo=[uww-mx01.datadirectnet.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM04FT059.eop-NAM04.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR19MB6637", "X-Mailman-Approved-At": "Mon, 24 Oct 2022 17:33:01 +0200", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add code to read the virtual address width for AMD processors.\nUpdated pci_device_iommu_support_va() to use glob to find iommu\ncapability files.\n\nSigned-off-by: Michael Piszczek <mpiszczek@ddn.com>\n---\n drivers/bus/pci/linux/pci.c | 58 ++++++++++++++++++++++---------------\n 1 file changed, 35 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c\nindex ebd1395502..291090ba7b 100644\n--- a/drivers/bus/pci/linux/pci.c\n+++ b/drivers/bus/pci/linux/pci.c\n@@ -4,6 +4,7 @@\n \n #include <string.h>\n #include <dirent.h>\n+#include <glob.h>\n \n #include <rte_log.h>\n #include <rte_pci.h>\n@@ -480,42 +481,53 @@ rte_pci_scan(void)\n }\n \n #if defined(RTE_ARCH_X86)\n+\n bool\n pci_device_iommu_support_va(const struct rte_pci_device *dev)\n {\n-#define VTD_CAP_MGAW_SHIFT\t16\n-#define VTD_CAP_MGAW_MASK\t(0x3fULL << VTD_CAP_MGAW_SHIFT)\n+#define VTD_CAP_MGAW_SHIFT 16\n+#define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT)\n+#define RD_AMD_CAP_VASIZE_SHIFT 15\n+#define RD_AMD_CAP_VASIZE_MASK (0x7F << RD_AMD_CAP_VASIZE_SHIFT)\n+\tint rc;\n \tconst struct rte_pci_addr *addr = &dev->addr;\n-\tchar filename[PATH_MAX];\n-\tFILE *fp;\n-\tuint64_t mgaw, vtd_cap_reg = 0;\n+\tchar pattern[PATH_MAX];\n+\tglob_t glob_results;\n+\tuint64_t mgaw = 0;\n \n-\tsnprintf(filename, sizeof(filename),\n-\t\t \"%s/\" PCI_PRI_FMT \"/iommu/intel-iommu/cap\",\n+\tsnprintf(pattern, sizeof(pattern),\n+\t\t \"%s/\" PCI_PRI_FMT \"/iommu/*-iommu/cap\",\n \t\t rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid,\n \t\t addr->function);\n \n-\tfp = fopen(filename, \"r\");\n-\tif (fp == NULL) {\n-\t\t/* We don't have an Intel IOMMU, assume VA supported */\n-\t\tif (errno == ENOENT)\n-\t\t\treturn true;\n+\trc = glob(pattern, 0, NULL, &glob_results);\n+\tif (rc != 0 && glob_results.gl_pathc == 1) {\n+\t\tconst char *filename = glob_results.gl_pathv[0];\n+\t\tFILE *fp = fopen(filename, \"r\");\n \n-\t\tRTE_LOG(ERR, EAL, \"%s(): can't open %s: %s\\n\",\n-\t\t\t__func__, filename, strerror(errno));\n-\t\treturn false;\n-\t}\n+\t\tif (fp != NULL) {\n+\t\t\tuint64_t cap_reg = 0;\n \n-\t/* We have an Intel IOMMU */\n-\tif (fscanf(fp, \"%\" PRIx64, &vtd_cap_reg) != 1) {\n-\t\tRTE_LOG(ERR, EAL, \"%s(): can't read %s\\n\", __func__, filename);\n-\t\tfclose(fp);\n-\t\treturn false;\n+\t\t\tif (fscanf(fp, \"%\" PRIx64, &cap_reg) != 1) {\n+\t\t\t\tRTE_LOG(ERR, EAL, \"%s(): can't read %s\\n\", __func__, filename);\n+\t\t\t}\n+\t\t\telse if (strstr(filename, \"intel-iommu\") != NULL) {\n+\t\t\t\t/* We have an Intel IOMMU */\n+\t\t\t\tmgaw = ((cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1;\n+\t\t\t}\n+\t\t\telse if (strstr(filename, \"amd-iommu\") != NULL) {\n+\t\t\t\t/* We have an Amd IOMMU */\n+\t\t\t\tmgaw = ((cap_reg & RD_AMD_CAP_VASIZE_MASK) >> RD_AMD_CAP_VASIZE_SHIFT) + 1;\n+\t\t\t}\n+\n+\t\t\tfclose(fp);\n+\t\t}\n \t}\n \n-\tfclose(fp);\n+\tglobfree(&glob_results);\n \n-\tmgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1;\n+\tif (mgaw == 0)\n+\t\treturn false;\n \n \t/*\n \t * Assuming there is no limitation by now. We can not know at this point\n", "prefixes": [ "v5" ] }