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GET /api/patches/118820/?format=api
{ "id": 118820, "url": "http://patches.dpdk.org/api/patches/118820/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221020155749.16643-14-valex@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221020155749.16643-14-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221020155749.16643-14-valex@nvidia.com", "date": "2022-10-20T15:57:43", "name": "[v6,13/18] net/mlx5/hws: Add HWS table object", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "9791a1e2ecdeb78c5297429dfbc0c403fa274881", "submitter": { "id": 2858, "url": "http://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221020155749.16643-14-valex@nvidia.com/mbox/", "series": [ { "id": 25345, "url": "http://patches.dpdk.org/api/series/25345/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25345", "date": "2022-10-20T15:57:30", "name": "net/mlx5: Add HW steering low level support", "version": 6, "mbox": "http://patches.dpdk.org/series/25345/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/118820/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/118820/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=Nen1Tr7wVdpIR0y0x2zPL0h+T5gYqlyf/cG1OZhLtYhfY+eZ9MrJI8YVR1jBBuchY7D0TGSz+pv73kdDa6TqZ/L7MeLnVIrPS9qnbURXY+ties0btpheIgQcNZVgsN0AphAmYmcXYJsFiyHZTXE5ksuJVWQ+a/r7v1snSEpeYes6qU0Q6P1mkU7Ru37XsSxeg4VfPmbZoR+weOULEn49y31d+yUQYT/AR+4xLUcnE9X8oNNrYPuztJpceyflNHdFX9YhFAXvagJ4B7vxTfR5smVtNcsa6/W+w1fRI/4A1WRnvy/sqsM5EX+66n8lODGJmEwy63R5TD0DHt4kfADsCw==", "X-MS-Exchange-Authentication-Results": "spf=none (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=fail action=oreject header.from=nvidia.com;", "Received-SPF": "None (protection.outlook.com: nvidia.com does not designate\n permitted sender hosts)", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, Erez Shitrit <erezsh@nvidia.com>", "Subject": "[v6 13/18] net/mlx5/hws: Add HWS table object", "Date": "Thu, 20 Oct 2022 18:57:43 +0300", "Message-ID": "<20221020155749.16643-14-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221020155749.16643-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221020155749.16643-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT028:EE_|DS7PR12MB5935:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5df2022a-8ca8-4acd-9124-08dab2b4145b", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n lVG9EYJq1S2Xeoo5io0E/t5ClZMP0mMf4Ff3GiCqX0zcsSQEPYvHfqa35dHcY9yGDeDRoxH9z3l1kTtUdNp3CZWCLpPiiQObYGL56C3P+tXavagzHeDHYU4RYEawBDP8r4KWUpCjKcLTgJ1SCANd7iwdSiZrs3AyjjRAKhmfkTmxx3qLPyumKP3bXf/BF/Mz68JGwDQVEEYiVomCN/FvRfpyB4DCltP5azqizREIL8gXNVdK+ak+PTHbazBz2RG/t2viQdDiywiJCD4wQtkhi6arftM+tlahaUeD7c2wvdjFo1/PN5b7TkIKfDhUierqUTPemEYUJBk4TaG/eK11MoN36bYNYXuicBwZQMZiwLcKubVCD8ukWXdlrMAFW28LkT3dGtSplxbTmuzYwthhctGfjSV1EZjAPP1yxT3NPQTqGgBD9iSk26ibaf//esyUwJonLHhBi6STSP8CSButkO9+tc3MVCMtjVjBrjb2cr66hQyTjdS4raEAJQlcPuDhFeBSK3v74fM8sRuaObil6MYRKUfk53O+HKNiSBV+oLSa/1lIF00o1iNY6U/SAVVgbtC/+agrDIDbkFbQU8g9E4Y5NcYH1fVnaZSt0eXlv+/uaIbUndoESuQYJHJssCXGQ4gQu6971DWFsNwARi/3bvrXOnr/DLLHENESkvc3RKRfk2KjAXBwP/IPucXyMXXyL7eH1e9+Y6zhcsoZV+Gx1BOiKPjOIqe6b4FGZ07AQwDQCMykAcljG6XfGczXmN89QUbybDS2UqrF/FJe3dEm6g==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(136003)(396003)(346002)(39860400002)(376002)(451199015)(46966006)(40470700004)(36840700001)(8676002)(70206006)(5660300002)(7696005)(4326008)(7636003)(107886003)(6666004)(70586007)(26005)(36756003)(6286002)(8936002)(356005)(41300700001)(6636002)(110136005)(54906003)(316002)(336012)(86362001)(40480700001)(47076005)(426003)(55016003)(83380400001)(2906002)(186003)(16526019)(1076003)(40460700003)(82740400003)(36860700001)(2616005)(82310400005)(478600001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Oct 2022 15:59:32.9405 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5df2022a-8ca8-4acd-9124-08dab2b4145b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT028.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS7PR12MB5935", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "HWS table resides under the context object, each context can\nhave multiple tables with different steering types RX/TX/FDB.\nThe table is not only a logical object but it is also represented\nin the HW, packets can be steered to the table and from there\nto other tables.\n\nSigned-off-by: Erez Shitrit <erezsh@nvidia.com>\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_table.c | 248 ++++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_table.h | 44 +++++\n 2 files changed, 292 insertions(+)\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_table.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_table.h", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_table.c b/drivers/net/mlx5/hws/mlx5dr_table.c\nnew file mode 100644\nindex 0000000000..d3f77e4780\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_table.c\n@@ -0,0 +1,248 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#include \"mlx5dr_internal.h\"\n+\n+static void mlx5dr_table_init_next_ft_attr(struct mlx5dr_table *tbl,\n+\t\t\t\t\t struct mlx5dr_cmd_ft_create_attr *ft_attr)\n+{\n+\tft_attr->type = tbl->fw_ft_type;\n+\tif (tbl->type == MLX5DR_TABLE_TYPE_FDB)\n+\t\tft_attr->level = tbl->ctx->caps->fdb_ft.max_level - 1;\n+\telse\n+\t\tft_attr->level = tbl->ctx->caps->nic_ft.max_level - 1;\n+\tft_attr->rtc_valid = true;\n+}\n+\n+/* Call this under ctx->ctrl_lock */\n+static int\n+mlx5dr_table_up_default_fdb_miss_tbl(struct mlx5dr_table *tbl)\n+{\n+\tstruct mlx5dr_cmd_ft_create_attr ft_attr = {0};\n+\tstruct mlx5dr_cmd_forward_tbl *default_miss;\n+\tstruct mlx5dr_context *ctx = tbl->ctx;\n+\tuint8_t tbl_type = tbl->type;\n+\tuint32_t vport;\n+\n+\tif (tbl->type != MLX5DR_TABLE_TYPE_FDB)\n+\t\treturn 0;\n+\n+\tif (ctx->common_res[tbl_type].default_miss) {\n+\t\tctx->common_res[tbl_type].default_miss->refcount++;\n+\t\treturn 0;\n+\t}\n+\n+\tft_attr.type = tbl->fw_ft_type;\n+\tft_attr.level = tbl->ctx->caps->fdb_ft.max_level; /* The last level */\n+\tft_attr.rtc_valid = false;\n+\n+\tassert(ctx->caps->eswitch_manager);\n+\tvport = ctx->caps->eswitch_manager_vport_number;\n+\n+\tdefault_miss = mlx5dr_cmd_miss_ft_create(ctx->ibv_ctx, &ft_attr, vport);\n+\tif (!default_miss) {\n+\t\tDR_LOG(ERR, \"Failed to default miss table type: 0x%x\", tbl_type);\n+\t\treturn rte_errno;\n+\t}\n+\n+\tctx->common_res[tbl_type].default_miss = default_miss;\n+\tctx->common_res[tbl_type].default_miss->refcount++;\n+\treturn 0;\n+}\n+\n+/* Called under pthread_spin_lock(&ctx->ctrl_lock) */\n+static void mlx5dr_table_down_default_fdb_miss_tbl(struct mlx5dr_table *tbl)\n+{\n+\tstruct mlx5dr_cmd_forward_tbl *default_miss;\n+\tstruct mlx5dr_context *ctx = tbl->ctx;\n+\tuint8_t tbl_type = tbl->type;\n+\n+\tif (tbl->type != MLX5DR_TABLE_TYPE_FDB)\n+\t\treturn;\n+\n+\tdefault_miss = ctx->common_res[tbl_type].default_miss;\n+\tif (--default_miss->refcount)\n+\t\treturn;\n+\n+\tmlx5dr_cmd_miss_ft_destroy(default_miss);\n+\n+\tsimple_free(default_miss);\n+\tctx->common_res[tbl_type].default_miss = NULL;\n+}\n+\n+static int\n+mlx5dr_table_connect_to_default_miss_tbl(struct mlx5dr_table *tbl,\n+\t\t\t\t\t struct mlx5dr_devx_obj *ft)\n+{\n+\tstruct mlx5dr_cmd_ft_modify_attr ft_attr = {0};\n+\tint ret;\n+\n+\tassert(tbl->type == MLX5DR_TABLE_TYPE_FDB);\n+\n+\tmlx5dr_cmd_set_attr_connect_miss_tbl(tbl->ctx,\n+\t\t\t\t\t tbl->fw_ft_type,\n+\t\t\t\t\t tbl->type,\n+\t\t\t\t\t &ft_attr);\n+\n+\t/* Connect to next */\n+\tret = mlx5dr_cmd_flow_table_modify(ft, &ft_attr);\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to connect FT to default FDB FT\");\n+\t\treturn errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+struct mlx5dr_devx_obj *\n+mlx5dr_table_create_default_ft(struct mlx5dr_table *tbl)\n+{\n+\tstruct mlx5dr_cmd_ft_create_attr ft_attr = {0};\n+\tstruct mlx5dr_devx_obj *ft_obj;\n+\tint ret;\n+\n+\tmlx5dr_table_init_next_ft_attr(tbl, &ft_attr);\n+\n+\tft_obj = mlx5dr_cmd_flow_table_create(tbl->ctx->ibv_ctx, &ft_attr);\n+\tif (ft_obj && tbl->type == MLX5DR_TABLE_TYPE_FDB) {\n+\t\t/* Take/create ref over the default miss */\n+\t\tret = mlx5dr_table_up_default_fdb_miss_tbl(tbl);\n+\t\tif (ret) {\n+\t\t\tDR_LOG(ERR, \"Failed to get default fdb miss\");\n+\t\t\tgoto free_ft_obj;\n+\t\t}\n+\t\tret = mlx5dr_table_connect_to_default_miss_tbl(tbl, ft_obj);\n+\t\tif (ret) {\n+\t\t\tDR_LOG(ERR, \"Failed connecting to default miss tbl\");\n+\t\t\tgoto down_miss_tbl;\n+\t\t}\n+\t}\n+\n+\treturn ft_obj;\n+\n+down_miss_tbl:\n+\tmlx5dr_table_down_default_fdb_miss_tbl(tbl);\n+free_ft_obj:\n+\tmlx5dr_cmd_destroy_obj(ft_obj);\n+\treturn NULL;\n+}\n+\n+void mlx5dr_table_destroy_default_ft(struct mlx5dr_table *tbl,\n+\t\t\t\t struct mlx5dr_devx_obj *ft_obj)\n+{\n+\tmlx5dr_table_down_default_fdb_miss_tbl(tbl);\n+\tmlx5dr_cmd_destroy_obj(ft_obj);\n+}\n+\n+static int mlx5dr_table_init(struct mlx5dr_table *tbl)\n+{\n+\tstruct mlx5dr_context *ctx = tbl->ctx;\n+\tint ret;\n+\n+\tif (mlx5dr_table_is_root(tbl))\n+\t\treturn 0;\n+\n+\tif (!(tbl->ctx->flags & MLX5DR_CONTEXT_FLAG_HWS_SUPPORT)) {\n+\t\tDR_LOG(ERR, \"HWS not supported, cannot create mlx5dr_table\");\n+\t\trte_errno = EOPNOTSUPP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tswitch (tbl->type) {\n+\tcase MLX5DR_TABLE_TYPE_NIC_RX:\n+\t\ttbl->fw_ft_type = FS_FT_NIC_RX;\n+\t\tbreak;\n+\tcase MLX5DR_TABLE_TYPE_NIC_TX:\n+\t\ttbl->fw_ft_type = FS_FT_NIC_TX;\n+\t\tbreak;\n+\tcase MLX5DR_TABLE_TYPE_FDB:\n+\t\ttbl->fw_ft_type = FS_FT_FDB;\n+\t\tbreak;\n+\tdefault:\n+\t\tassert(0);\n+\t\tbreak;\n+\t}\n+\n+\tpthread_spin_lock(&ctx->ctrl_lock);\n+\ttbl->ft = mlx5dr_table_create_default_ft(tbl);\n+\tif (!tbl->ft) {\n+\t\tDR_LOG(ERR, \"Failed to create flow table devx object\");\n+\t\tpthread_spin_unlock(&ctx->ctrl_lock);\n+\t\treturn rte_errno;\n+\t}\n+\n+\tret = mlx5dr_action_get_default_stc(ctx, tbl->type);\n+\tif (ret)\n+\t\tgoto tbl_destroy;\n+\tpthread_spin_unlock(&ctx->ctrl_lock);\n+\n+\treturn 0;\n+\n+tbl_destroy:\n+\tmlx5dr_table_destroy_default_ft(tbl, tbl->ft);\n+\tpthread_spin_unlock(&ctx->ctrl_lock);\n+\treturn rte_errno;\n+}\n+\n+static void mlx5dr_table_uninit(struct mlx5dr_table *tbl)\n+{\n+\tif (mlx5dr_table_is_root(tbl))\n+\t\treturn;\n+\tpthread_spin_lock(&tbl->ctx->ctrl_lock);\n+\tmlx5dr_action_put_default_stc(tbl->ctx, tbl->type);\n+\tmlx5dr_table_destroy_default_ft(tbl, tbl->ft);\n+\tpthread_spin_unlock(&tbl->ctx->ctrl_lock);\n+}\n+\n+struct mlx5dr_table *mlx5dr_table_create(struct mlx5dr_context *ctx,\n+\t\t\t\t\t struct mlx5dr_table_attr *attr)\n+{\n+\tstruct mlx5dr_table *tbl;\n+\tint ret;\n+\n+\tif (attr->type > MLX5DR_TABLE_TYPE_FDB) {\n+\t\tDR_LOG(ERR, \"Invalid table type %d\", attr->type);\n+\t\treturn NULL;\n+\t}\n+\n+\ttbl = simple_malloc(sizeof(*tbl));\n+\tif (!tbl) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\ttbl->ctx = ctx;\n+\ttbl->type = attr->type;\n+\ttbl->level = attr->level;\n+\tLIST_INIT(&tbl->head);\n+\n+\tret = mlx5dr_table_init(tbl);\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to initialise table\");\n+\t\tgoto free_tbl;\n+\t}\n+\n+\tpthread_spin_lock(&ctx->ctrl_lock);\n+\tLIST_INSERT_HEAD(&ctx->head, tbl, next);\n+\tpthread_spin_unlock(&ctx->ctrl_lock);\n+\n+\treturn tbl;\n+\n+free_tbl:\n+\tsimple_free(tbl);\n+\treturn NULL;\n+}\n+\n+int mlx5dr_table_destroy(struct mlx5dr_table *tbl)\n+{\n+\tstruct mlx5dr_context *ctx = tbl->ctx;\n+\n+\tpthread_spin_lock(&ctx->ctrl_lock);\n+\tLIST_REMOVE(tbl, next);\n+\tpthread_spin_unlock(&ctx->ctrl_lock);\n+\tmlx5dr_table_uninit(tbl);\n+\tsimple_free(tbl);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_table.h b/drivers/net/mlx5/hws/mlx5dr_table.h\nnew file mode 100644\nindex 0000000000..786dddfaa4\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_table.h\n@@ -0,0 +1,44 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#ifndef MLX5DR_TABLE_H_\n+#define MLX5DR_TABLE_H_\n+\n+#define MLX5DR_ROOT_LEVEL 0\n+\n+struct mlx5dr_table {\n+\tstruct mlx5dr_context *ctx;\n+\tstruct mlx5dr_devx_obj *ft;\n+\tenum mlx5dr_table_type type;\n+\tuint32_t fw_ft_type;\n+\tuint32_t level;\n+\tLIST_HEAD(matcher_head, mlx5dr_matcher) head;\n+\tLIST_ENTRY(mlx5dr_table) next;\n+};\n+\n+static inline\n+uint32_t mlx5dr_table_get_res_fw_ft_type(enum mlx5dr_table_type tbl_type,\n+\t\t\t\t\t bool is_mirror)\n+{\n+\tif (tbl_type == MLX5DR_TABLE_TYPE_NIC_RX)\n+\t\treturn FS_FT_NIC_RX;\n+\telse if (tbl_type == MLX5DR_TABLE_TYPE_NIC_TX)\n+\t\treturn FS_FT_NIC_TX;\n+\telse if (tbl_type == MLX5DR_TABLE_TYPE_FDB)\n+\t\treturn is_mirror ? FS_FT_FDB_TX : FS_FT_FDB_RX;\n+\n+\tassert(0);\n+\treturn 0;\n+}\n+\n+static inline bool mlx5dr_table_is_root(struct mlx5dr_table *tbl)\n+{\n+\treturn (tbl->level == MLX5DR_ROOT_LEVEL);\n+}\n+\n+struct mlx5dr_devx_obj *mlx5dr_table_create_default_ft(struct mlx5dr_table *tbl);\n+\n+void mlx5dr_table_destroy_default_ft(struct mlx5dr_table *tbl,\n+\t\t\t\t struct mlx5dr_devx_obj *ft_obj);\n+#endif /* MLX5DR_TABLE_H_ */\n", "prefixes": [ "v6", "13/18" ] }