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GET /api/patches/118818/?format=api
{ "id": 118818, "url": "http://patches.dpdk.org/api/patches/118818/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221020155749.16643-13-valex@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221020155749.16643-13-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221020155749.16643-13-valex@nvidia.com", "date": "2022-10-20T15:57:42", "name": "[v6,12/18] net/mlx5/hws: Add HWS context object", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "860e4d9f6adcd641015a59c3b83ba2712e90c59a", "submitter": { "id": 2858, "url": "http://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221020155749.16643-13-valex@nvidia.com/mbox/", "series": [ { "id": 25345, "url": "http://patches.dpdk.org/api/series/25345/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25345", "date": "2022-10-20T15:57:30", "name": "net/mlx5: Add HW steering low level support", "version": 6, "mbox": "http://patches.dpdk.org/series/25345/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/118818/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/118818/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=h2lpQSsTXm41rV50H3J7f8X+7XYcP1qiXBf76EI6Z7x7B+EXFAb14cshc0mCxoT4oxe5fCgVw+qhYVBmBDYp+2vgKaPd7NAVmW7QMJa0bmpM3/QqoixgmgKqrohi0/2LZCBQ3ev40QtH+9rVjulVNUjh9/yaus0ZRxAkDqf9W7nIWaRTmOUCBYkRFML62wH78lkuhxmpDU55Cnpk7squtXzmmq4vgGq7wl+kOeCWp+1A90c3WS2ydxf0zsFkI8OJuUzbWDkOZ1QLVQ/1XFr08Fy6Vc4RNlIcVdjjh9tx2yrrnRoqHVPGM3B2E3Ieo3jSsAE9niHYTuON9jERD0zCBQ==", "X-MS-Exchange-Authentication-Results": "spf=none (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=fail action=oreject header.from=nvidia.com;", "Received-SPF": "None (protection.outlook.com: nvidia.com does not designate\n permitted sender hosts)", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v6 12/18] net/mlx5/hws: Add HWS context object", "Date": "Thu, 20 Oct 2022 18:57:42 +0300", "Message-ID": "<20221020155749.16643-13-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221020155749.16643-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221020155749.16643-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT093:EE_|BL1PR12MB5221:EE_", "X-MS-Office365-Filtering-Correlation-Id": "4b039f46-6190-4efc-2d34-08dab2b41026", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n snevyTBxiGy9JGobS5xs44VsV8GuUb0oWmZJwfe1MLj/RhlobbpCCd3u4HdcAm2HaP1uFFKkVxkC3ZpgVbGJCBSBsM2SoJ2NEXT/xNKkUkK37S7GZn1mlX0KfCM+EoSWrg4nyMj96Fip5UG0xh0Za40WhySAoD0lFgVxVa+ZwZJONmjFFJ8JWX64BZ0a1lnPJmWDXaIC2bjd1OvaIN7I8Um+UnjiVxxk90kQwVt4YndYlHvaRm1WjJgJRtQ3QlebZFTyjMohDvu8EcopfYsECqSb6/+c1M8Chs9gMeu5ZGu682qabjCLAOWpXt44S2eVmzkmYCDMYqSB1ZeCWFu/ADR6sNVc25UOy3NNS8idFIwXVie1AM7o8TufW842Ec0ESz9FwWlpI5/7TbaYRXZeOa2FHChgG++Gn6V1EJuv0DNcNLbxIlRUlZ+SG9Pywmwih4OCg3mpYda08X7RZro0bg6KVVG7dN6AS45H2TWqO5rCN5mrw0YkJceCWBNcDWjS17sKRWIpXKk3kbxQg1RBdkesuxLRmpkWgiHiETRKszomTe75k7/M5ToNnYUBilCK6QV17k1cd+ZyzD1aj6JaAVkEf4Re+3yN3rsdDNe/y5iEizKC+y2jM6B4gHidZQwPC250p92ObNqcWrOKLGsZl2IaWa84PcVsXDW6ftLZWS326qCKQZ7p4R9BAA8/kFtKnStyvLWq1phyD6n/roiUWylwq75KAhxZQ+UANO75P29W1v2N7I4+O2u0x3S8GNXdGC7D3wU8jvmWWtTfH2keOw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(136003)(39860400002)(376002)(396003)(346002)(451199015)(46966006)(40470700004)(36840700001)(66899015)(86362001)(478600001)(82310400005)(54906003)(110136005)(7636003)(316002)(6636002)(356005)(107886003)(6666004)(40460700003)(5660300002)(82740400003)(41300700001)(8676002)(4326008)(70206006)(70586007)(2906002)(26005)(83380400001)(47076005)(426003)(6286002)(1076003)(16526019)(186003)(336012)(8936002)(36860700001)(55016003)(36756003)(2616005)(7696005)(40480700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Oct 2022 15:59:25.9735 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4b039f46-6190-4efc-2d34-08dab2b41026", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT093.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5221", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Context is the first mlx5dr object created, all sub object:\ntable, matcher, rule, action are created using the context.\nThe context holds the capabilities and send queues used for\nconfiguring the offloads to the HW.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_context.c | 223 ++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_context.h | 40 +++++\n 2 files changed, 263 insertions(+)\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_context.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_context.h", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_context.c b/drivers/net/mlx5/hws/mlx5dr_context.c\nnew file mode 100644\nindex 0000000000..ae86694a51\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_context.c\n@@ -0,0 +1,223 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#include \"mlx5dr_internal.h\"\n+\n+static int mlx5dr_context_pools_init(struct mlx5dr_context *ctx)\n+{\n+\tstruct mlx5dr_pool_attr pool_attr = {0};\n+\tuint8_t max_log_sz;\n+\tint i;\n+\n+\tif (mlx5dr_pat_init_pattern_cache(&ctx->pattern_cache))\n+\t\treturn rte_errno;\n+\n+\t/* Create an STC pool per FT type */\n+\tpool_attr.pool_type = MLX5DR_POOL_TYPE_STC;\n+\tpool_attr.flags = MLX5DR_POOL_FLAGS_FOR_STC_POOL;\n+\tmax_log_sz = RTE_MIN(MLX5DR_POOL_STC_LOG_SZ, ctx->caps->stc_alloc_log_max);\n+\tpool_attr.alloc_log_sz = RTE_MAX(max_log_sz, ctx->caps->stc_alloc_log_gran);\n+\n+\tfor (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) {\n+\t\tpool_attr.table_type = i;\n+\t\tctx->stc_pool[i] = mlx5dr_pool_create(ctx, &pool_attr);\n+\t\tif (!ctx->stc_pool[i]) {\n+\t\t\tDR_LOG(ERR, \"Failed to allocate STC pool [%d]\", i);\n+\t\t\tgoto free_stc_pools;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+\n+free_stc_pools:\n+\tfor (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++)\n+\t\tif (ctx->stc_pool[i])\n+\t\t\tmlx5dr_pool_destroy(ctx->stc_pool[i]);\n+\n+\tmlx5dr_pat_uninit_pattern_cache(ctx->pattern_cache);\n+\n+\treturn rte_errno;\n+}\n+\n+static void mlx5dr_context_pools_uninit(struct mlx5dr_context *ctx)\n+{\n+\tint i;\n+\n+\tmlx5dr_pat_uninit_pattern_cache(ctx->pattern_cache);\n+\n+\tfor (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) {\n+\t\tif (ctx->stc_pool[i])\n+\t\t\tmlx5dr_pool_destroy(ctx->stc_pool[i]);\n+\t}\n+}\n+\n+static int mlx5dr_context_init_pd(struct mlx5dr_context *ctx,\n+\t\t\t\t struct ibv_pd *pd)\n+{\n+\tstruct mlx5dv_pd mlx5_pd = {0};\n+\tstruct mlx5dv_obj obj;\n+\tint ret;\n+\n+\tif (pd) {\n+\t\tctx->pd = pd;\n+\t} else {\n+\t\tctx->pd = mlx5_glue->alloc_pd(ctx->ibv_ctx);\n+\t\tif (!ctx->pd) {\n+\t\t\tDR_LOG(ERR, \"Failed to allocate PD\");\n+\t\t\trte_errno = errno;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\t\tctx->flags |= MLX5DR_CONTEXT_FLAG_PRIVATE_PD;\n+\t}\n+\n+\tobj.pd.in = ctx->pd;\n+\tobj.pd.out = &mlx5_pd;\n+\n+\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);\n+\tif (ret)\n+\t\tgoto free_private_pd;\n+\n+\tctx->pd_num = mlx5_pd.pdn;\n+\n+\treturn 0;\n+\n+free_private_pd:\n+\tif (ctx->flags & MLX5DR_CONTEXT_FLAG_PRIVATE_PD)\n+\t\tmlx5_glue->dealloc_pd(ctx->pd);\n+\n+\treturn ret;\n+}\n+\n+static int mlx5dr_context_uninit_pd(struct mlx5dr_context *ctx)\n+{\n+\tif (ctx->flags & MLX5DR_CONTEXT_FLAG_PRIVATE_PD)\n+\t\treturn mlx5_glue->dealloc_pd(ctx->pd);\n+\n+\treturn 0;\n+}\n+\n+static void mlx5dr_context_check_hws_supp(struct mlx5dr_context *ctx)\n+{\n+\tstruct mlx5dr_cmd_query_caps *caps = ctx->caps;\n+\n+\t/* HWS not supported on device / FW */\n+\tif (!caps->wqe_based_update) {\n+\t\tDR_LOG(INFO, \"Required HWS WQE based insertion cap not supported\");\n+\t\treturn;\n+\t}\n+\n+\t/* Current solution requires all rules to set reparse bit */\n+\tif ((!caps->nic_ft.reparse || !caps->fdb_ft.reparse) ||\n+\t !IS_BIT_SET(caps->rtc_reparse_mode, MLX5_IFC_RTC_REPARSE_ALWAYS)) {\n+\t\tDR_LOG(INFO, \"Required HWS reparse cap not supported\");\n+\t\treturn;\n+\t}\n+\n+\t/* FW/HW must support 8DW STE */\n+\tif (!IS_BIT_SET(caps->ste_format, MLX5_IFC_RTC_STE_FORMAT_8DW)) {\n+\t\tDR_LOG(INFO, \"Required HWS STE format not supported\");\n+\t\treturn;\n+\t}\n+\n+\t/* Adding rules by hash and by offset are requirements */\n+\tif (!IS_BIT_SET(caps->rtc_index_mode, MLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH) ||\n+\t !IS_BIT_SET(caps->rtc_index_mode, MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET)) {\n+\t\tDR_LOG(INFO, \"Required HWS RTC update mode not supported\");\n+\t\treturn;\n+\t}\n+\n+\t/* Support for SELECT definer ID is required */\n+\tif (!IS_BIT_SET(caps->definer_format_sup, MLX5_IFC_DEFINER_FORMAT_ID_SELECT)) {\n+\t\tDR_LOG(INFO, \"Required HWS Dynamic definer not supported\");\n+\t\treturn;\n+\t}\n+\n+\tctx->flags |= MLX5DR_CONTEXT_FLAG_HWS_SUPPORT;\n+}\n+\n+static int mlx5dr_context_init_hws(struct mlx5dr_context *ctx,\n+\t\t\t\t struct mlx5dr_context_attr *attr)\n+{\n+\tint ret;\n+\n+\tmlx5dr_context_check_hws_supp(ctx);\n+\n+\tif (!(ctx->flags & MLX5DR_CONTEXT_FLAG_HWS_SUPPORT))\n+\t\treturn 0;\n+\n+\tret = mlx5dr_context_init_pd(ctx, attr->pd);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mlx5dr_context_pools_init(ctx);\n+\tif (ret)\n+\t\tgoto uninit_pd;\n+\n+\tret = mlx5dr_send_queues_open(ctx, attr->queues, attr->queue_size);\n+\tif (ret)\n+\t\tgoto pools_uninit;\n+\n+\treturn 0;\n+\n+pools_uninit:\n+\tmlx5dr_context_pools_uninit(ctx);\n+uninit_pd:\n+\tmlx5dr_context_uninit_pd(ctx);\n+\treturn ret;\n+}\n+\n+static void mlx5dr_context_uninit_hws(struct mlx5dr_context *ctx)\n+{\n+\tif (!(ctx->flags & MLX5DR_CONTEXT_FLAG_HWS_SUPPORT))\n+\t\treturn;\n+\n+\tmlx5dr_send_queues_close(ctx);\n+\tmlx5dr_context_pools_uninit(ctx);\n+\tmlx5dr_context_uninit_pd(ctx);\n+}\n+\n+struct mlx5dr_context *mlx5dr_context_open(struct ibv_context *ibv_ctx,\n+\t\t\t\t\t struct mlx5dr_context_attr *attr)\n+{\n+\tstruct mlx5dr_context *ctx;\n+\tint ret;\n+\n+\tctx = simple_calloc(1, sizeof(*ctx));\n+\tif (!ctx) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\n+\tctx->ibv_ctx = ibv_ctx;\n+\tpthread_spin_init(&ctx->ctrl_lock, PTHREAD_PROCESS_PRIVATE);\n+\n+\tctx->caps = simple_calloc(1, sizeof(*ctx->caps));\n+\tif (!ctx->caps)\n+\t\tgoto free_ctx;\n+\n+\tret = mlx5dr_cmd_query_caps(ibv_ctx, ctx->caps);\n+\tif (ret)\n+\t\tgoto free_caps;\n+\n+\tret = mlx5dr_context_init_hws(ctx, attr);\n+\tif (ret)\n+\t\tgoto free_caps;\n+\n+\treturn ctx;\n+\n+free_caps:\n+\tsimple_free(ctx->caps);\n+free_ctx:\n+\tsimple_free(ctx);\n+\treturn NULL;\n+}\n+\n+int mlx5dr_context_close(struct mlx5dr_context *ctx)\n+{\n+\tmlx5dr_context_uninit_hws(ctx);\n+\tsimple_free(ctx->caps);\n+\tpthread_spin_destroy(&ctx->ctrl_lock);\n+\tsimple_free(ctx);\n+\treturn 0;\n+}\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_context.h b/drivers/net/mlx5/hws/mlx5dr_context.h\nnew file mode 100644\nindex 0000000000..b0c7802daf\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_context.h\n@@ -0,0 +1,40 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#ifndef MLX5DR_CONTEXT_H_\n+#define MLX5DR_CONTEXT_H_\n+\n+enum mlx5dr_context_flags {\n+\tMLX5DR_CONTEXT_FLAG_HWS_SUPPORT = 1 << 0,\n+\tMLX5DR_CONTEXT_FLAG_PRIVATE_PD = 1 << 1,\n+};\n+\n+enum mlx5dr_context_shared_stc_type {\n+\tMLX5DR_CONTEXT_SHARED_STC_DECAP = 0,\n+\tMLX5DR_CONTEXT_SHARED_STC_POP = 1,\n+\tMLX5DR_CONTEXT_SHARED_STC_MAX = 2,\n+};\n+\n+struct mlx5dr_context_common_res {\n+\tstruct mlx5dr_action_default_stc *default_stc;\n+\tstruct mlx5dr_action_shared_stc *shared_stc[MLX5DR_CONTEXT_SHARED_STC_MAX];\n+\tstruct mlx5dr_cmd_forward_tbl *default_miss;\n+};\n+\n+struct mlx5dr_context {\n+\tstruct ibv_context *ibv_ctx;\n+\tstruct mlx5dr_cmd_query_caps *caps;\n+\tstruct ibv_pd *pd;\n+\tuint32_t pd_num;\n+\tstruct mlx5dr_pool *stc_pool[MLX5DR_TABLE_TYPE_MAX];\n+\tstruct mlx5dr_context_common_res common_res[MLX5DR_TABLE_TYPE_MAX];\n+\tstruct mlx5dr_pattern_cache *pattern_cache;\n+\tpthread_spinlock_t ctrl_lock;\n+\tenum mlx5dr_context_flags flags;\n+\tstruct mlx5dr_send_engine *send_queue;\n+\tsize_t queues;\n+\tLIST_HEAD(table_head, mlx5dr_table) head;\n+};\n+\n+#endif /* MLX5DR_CONTEXT_H_ */\n", "prefixes": [ "v6", "12/18" ] }