Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/118815/?format=api
{ "id": 118815, "url": "http://patches.dpdk.org/api/patches/118815/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221020155749.16643-8-valex@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221020155749.16643-8-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221020155749.16643-8-valex@nvidia.com", "date": "2022-10-20T15:57:37", "name": "[v6,07/18] net/mlx5: Add additional glue functions for HWS", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6cedee354968f5282c16371ae27c82af13949a05", "submitter": { "id": 2858, "url": "http://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221020155749.16643-8-valex@nvidia.com/mbox/", "series": [ { "id": 25345, "url": "http://patches.dpdk.org/api/series/25345/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25345", "date": "2022-10-20T15:57:30", "name": "net/mlx5: Add HW steering low level support", "version": 6, "mbox": "http://patches.dpdk.org/series/25345/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/118815/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/118815/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 313EEA0553;\n\tThu, 20 Oct 2022 17:59:56 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7034442BA5;\n\tThu, 20 Oct 2022 17:59:23 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2049.outbound.protection.outlook.com [40.107.244.49])\n by mails.dpdk.org (Postfix) with ESMTP id 094F742B80\n for <dev@dpdk.org>; Thu, 20 Oct 2022 17:59:21 +0200 (CEST)", "from BN0PR04CA0032.namprd04.prod.outlook.com (2603:10b6:408:e8::7)\n by MW4PR12MB7014.namprd12.prod.outlook.com (2603:10b6:303:218::8) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.32; Thu, 20 Oct\n 2022 15:59:19 +0000", "from BN8NAM11FT084.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:e8:cafe::aa) by BN0PR04CA0032.outlook.office365.com\n (2603:10b6:408:e8::7) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.35 via Frontend\n Transport; Thu, 20 Oct 2022 15:59:18 +0000", "from mail.nvidia.com (216.228.117.161) by\n BN8NAM11FT084.mail.protection.outlook.com (10.13.176.169) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.5746.16 via Frontend Transport; Thu, 20 Oct 2022 15:59:18 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 20 Oct\n 2022 08:59:03 -0700", "from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 20 Oct\n 2022 08:59:00 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=B6RM9Fp9jtKxFi9SS83S2/sV0rOiF9CU9G8cLpr/s8M42RFMyMWsd6ECTCcRC1LArYS0QUqGkidyU0Pbolkj3gJPavRGZBtoVHKaekVjckk5swiQf+woYbPBHiVKTfl9EGYWpVSrNvbEuOIOBot0iNrew3dt5k2G08wWbqZdam5BB8ZMDXVyFkp8YXIVYeR2rUQ5xhvmv4i7TnOdSbyOCC0SUObabesKSMT4olhJSY+835HVZVqt7u21bKhA17AVinh8num+eojYSWrovxCHZ6j0mVzxTLxj/or3O4tB3586a1Nyh2SVlCQkl/jfjVreyMgPDXEjVzFreZKcJ8KBXw==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=cDNSzfVc0XN3um1BBnxkm0Fdp7RzPaWhJtUOcxQpE4U=;\n b=WPlS3/K9KGht5h1llnTmzt9CcfKnI8zN2yPxM0OqxeSW+2O4ewfw6lEbhQL+yXNkvb3Qe2Xd6X0bID/w1Yzg2DPbk9/xQ053Mxg9pNKgg6TyLAoeiPB54INBdO/GPoIVuL99guiPZAtQLFHslkou322UATPsob/q+GNgXRHlm/2oQNBUfQVl/zZcWHsJuYjzo02ZlNS0F4mggffcXKwEKmksYrKYtrFZiYo8MwGJ8YPe1KHqGpPeV7mQc8A+YRlxfsc1ZVtNkI7d/ckWK4vtEbIWWm6HIiDl7bHCXT6iYreaLkdNCL49VWAub5ZTXwis3QaNhAr+lefZjE9anxF6Sg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=none (sender ip is\n 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=fail (p=reject sp=reject pct=100) action=oreject\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=cDNSzfVc0XN3um1BBnxkm0Fdp7RzPaWhJtUOcxQpE4U=;\n b=ngtPdCuqErEXp3VBYvDvZM4XX51sipPkNKtPabE0VKkGnbtpzjRkkNxgkKEiiVXhaoS9XsYDV+PrO9Wd8JQgkh9QVOl3i3qZqC7ukb7EDYccyNzzIVpGL4RUgcbNag2u7dpGYLiyDLqZYXBxThJ7q0SV5X0CfkkuJGsmO6bdVWJsucXgJjcInYTOZqWjd/7xj+gqM/hiciXB2eYp+Ok8hf8fgxdZwNh1RJeSJSkinm9nhe2DzmOgqve1Z4Dn8DZtstRmz+e/EYU2qSjTuHaHJh+CuRaSmTZMr0OwoTGhs8r19W7qtoO1CyNn/1OxaLx8lAALbLwwCEbcItD+kBW1gA==", "X-MS-Exchange-Authentication-Results": "spf=none (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=fail action=oreject header.from=nvidia.com;", "Received-SPF": "None (protection.outlook.com: nvidia.com does not designate\n permitted sender hosts)", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v6 07/18] net/mlx5: Add additional glue functions for HWS", "Date": "Thu, 20 Oct 2022 18:57:37 +0300", "Message-ID": "<20221020155749.16643-8-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221020155749.16643-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221020155749.16643-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT084:EE_|MW4PR12MB7014:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0c5faa7f-4404-4bc0-f163-08dab2b40bc6", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n P1x5JHvSlmfV/0jdnpYhOO9Aub8yYwexdOwm/EaxIQJasJowGeJxOSo+fIw3jaPXQ8mDkMiEI13RoNT4FesVrDqLOmCWYXq/aEpKdzOCNnAh4VinzK5S4I8lt04ycsntayHCbIi66SHQW7sNQRueXUIORcrSGGJDO7q4Cm2ZGRgZxQW5+49W/dcJl5tTm/lq7qongO4+aeecyY6T63PEmq8qKw7RTnlhHlEOvGPFT2QQ3MK23BRHnNGJWTmhEdshuNnWwkgXQtAcRSFLn0j54IN6Ygh1xBpbN68F+9gwn0ixWl9Eg6ksFjKxI7kIYPy44TEGgORYv1YvUaZr1Jq0Ng11IciKoDoOfeYLIGldNFdulA9xCQA4S8Od+vHk16cHYL/S9WzLY2HMMTUxwKzqwvYDX2e1bbPVREdH8kLDhiiIxqYVZbbVQ1/Czau6XrAzUDmLjrgUcjm3z1/ad1KTYGA+twMhatiaxM5QHswQJShPMCPSxgAxIgh7Es6ixiU2eLwX/d1Kz7hVUhwzEpg8T9NoCX/4LHPHlOJsKj5h7IaKUggdzot0QANzpzmF/W5SZZsjpXbwnGxgFXdXVwesYUVVEuO4gMBynrK06wnXaji60tNE/i2U4RFTEmmBhzQyeXmSzyu5Bd69vFLUtngorzG7AMm5hm7zQDpfY+Cp6QTb1eDocrjpcJQ9LgUwboUd91qukTAPA7DQMi3lKchFHmwlyI7d3qYzIpdhxUhtQN4iWbYgwfWktJq/RogGPEgKdwz94RoEBqFciyN7rEowMw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(346002)(396003)(136003)(376002)(39860400002)(451199015)(40470700004)(36840700001)(46966006)(70206006)(107886003)(36756003)(16526019)(2906002)(6666004)(8936002)(4326008)(40480700001)(5660300002)(26005)(40460700003)(41300700001)(336012)(7636003)(186003)(82310400005)(2616005)(86362001)(1076003)(6286002)(478600001)(8676002)(55016003)(356005)(426003)(30864003)(83380400001)(70586007)(82740400003)(7696005)(47076005)(54906003)(36860700001)(316002)(110136005)(6636002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Oct 2022 15:59:18.5447 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0c5faa7f-4404-4bc0-f163-08dab2b40bc6", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT084.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW4PR12MB7014", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add missing glue support for HWS mlx5dr layer. The new glue\nfunctions are needed for mlx5dv create matcher and action,\nwhich are used as the kernel root table as well as for\ncapabilities query like device name and ports info.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/common/mlx5/linux/mlx5_glue.c | 121 ++++++++++++++++++++++++--\n drivers/common/mlx5/linux/mlx5_glue.h | 17 ++++\n 2 files changed, 131 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/linux/mlx5_glue.c b/drivers/common/mlx5/linux/mlx5_glue.c\nindex b954df0784..702eb36b62 100644\n--- a/drivers/common/mlx5/linux/mlx5_glue.c\n+++ b/drivers/common/mlx5/linux/mlx5_glue.c\n@@ -111,6 +111,12 @@ mlx5_glue_query_device_ex(struct ibv_context *context,\n \treturn ibv_query_device_ex(context, input, attr);\n }\n \n+static const char *\n+mlx5_glue_get_device_name(struct ibv_device *device)\n+{\n+\treturn ibv_get_device_name(device);\n+}\n+\n static int\n mlx5_glue_query_rt_values_ex(struct ibv_context *context,\n \t\t\t struct ibv_values_ex *values)\n@@ -620,6 +626,20 @@ mlx5_glue_dv_create_qp(struct ibv_context *context,\n #endif\n }\n \n+static void *\n+__mlx5_glue_dv_create_flow_matcher(struct ibv_context *context,\n+\t\tstruct mlx5dv_flow_matcher_attr *matcher_attr)\n+{\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\treturn mlx5dv_create_flow_matcher(context, matcher_attr);\n+#else\n+\t(void)context;\n+\t(void)matcher_attr;\n+\terrno = ENOTSUP;\n+\treturn NULL;\n+#endif\n+}\n+\n static void *\n mlx5_glue_dv_create_flow_matcher(struct ibv_context *context,\n \t\t\t\t struct mlx5dv_flow_matcher_attr *matcher_attr,\n@@ -633,7 +653,7 @@ mlx5_glue_dv_create_flow_matcher(struct ibv_context *context,\n \t\t\t\t\tmatcher_attr->match_mask);\n #else\n \t(void)tbl;\n-\treturn mlx5dv_create_flow_matcher(context, matcher_attr);\n+\treturn __mlx5_glue_dv_create_flow_matcher(context, matcher_attr);\n #endif\n #else\n \t(void)context;\n@@ -644,6 +664,26 @@ mlx5_glue_dv_create_flow_matcher(struct ibv_context *context,\n #endif\n }\n \n+static void *\n+__mlx5_glue_dv_create_flow(void *matcher,\n+\t\t\t void *match_value,\n+\t\t\t size_t num_actions,\n+\t\t\t void *actions)\n+{\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\treturn mlx5dv_create_flow(matcher,\n+\t\t\t\t match_value,\n+\t\t\t\t num_actions,\n+\t\t\t\t (struct mlx5dv_flow_action_attr *)actions);\n+#else\n+\t(void)matcher;\n+\t(void)match_value;\n+\t(void)num_actions;\n+\t(void)actions;\n+\treturn NULL;\n+#endif\n+}\n+\n static void *\n mlx5_glue_dv_create_flow(void *matcher,\n \t\t\t void *match_value,\n@@ -663,8 +703,8 @@ mlx5_glue_dv_create_flow(void *matcher,\n \tfor (i = 0; i < num_actions; i++)\n \t\tactions_attr[i] =\n \t\t\t*((struct mlx5dv_flow_action_attr *)(actions[i]));\n-\treturn mlx5dv_create_flow(matcher, match_value,\n-\t\t\t\t num_actions, actions_attr);\n+\treturn __mlx5_glue_dv_create_flow(matcher, match_value,\n+\t\t\t\t\t num_actions, actions_attr);\n #endif\n #else\n \t(void)matcher;\n@@ -735,6 +775,26 @@ mlx5_glue_dv_create_flow_action_dest_devx_tir(void *tir)\n #endif\n }\n \n+static void *\n+__mlx5_glue_dv_create_flow_action_modify_header\n+\t\t\t\t\t(struct ibv_context *ctx,\n+\t\t\t\t\t size_t actions_sz,\n+\t\t\t\t\t uint64_t actions[],\n+\t\t\t\t\t enum mlx5dv_flow_table_type ft_type)\n+{\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\treturn mlx5dv_create_flow_action_modify_header\n+\t\t(ctx, actions_sz, actions, ft_type);\n+#else\n+\t(void)ctx;\n+\t(void)ft_type;\n+\t(void)actions_sz;\n+\t(void)actions;\n+\terrno = ENOTSUP;\n+\treturn NULL;\n+#endif\n+}\n+\n static void *\n mlx5_glue_dv_create_flow_action_modify_header\n \t\t\t\t\t(struct ibv_context *ctx,\n@@ -758,7 +818,7 @@ mlx5_glue_dv_create_flow_action_modify_header\n \tif (!action)\n \t\treturn NULL;\n \taction->type = MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;\n-\taction->action = mlx5dv_create_flow_action_modify_header\n+\taction->action = __mlx5_glue_dv_create_flow_action_modify_header\n \t\t(ctx, actions_sz, actions, ft_type);\n \treturn action;\n #endif\n@@ -774,6 +834,27 @@ mlx5_glue_dv_create_flow_action_modify_header\n #endif\n }\n \n+static void *\n+__mlx5_glue_dv_create_flow_action_packet_reformat\n+\t\t(struct ibv_context *ctx,\n+\t\t size_t data_sz, void *data,\n+\t\t enum mlx5dv_flow_action_packet_reformat_type reformat_type,\n+\t\t enum mlx5dv_flow_table_type ft_type)\n+{\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\treturn mlx5dv_create_flow_action_packet_reformat\n+\t\t(ctx, data_sz, data, reformat_type, ft_type);\n+#else\n+\t(void)ctx;\n+\t(void)reformat_type;\n+\t(void)ft_type;\n+\t(void)data_sz;\n+\t(void)data;\n+\terrno = ENOTSUP;\n+\treturn NULL;\n+#endif\n+}\n+\n static void *\n mlx5_glue_dv_create_flow_action_packet_reformat\n \t\t(struct ibv_context *ctx,\n@@ -798,7 +879,7 @@ mlx5_glue_dv_create_flow_action_packet_reformat\n \tif (!action)\n \t\treturn NULL;\n \taction->type = MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;\n-\taction->action = mlx5dv_create_flow_action_packet_reformat\n+\taction->action = __mlx5_glue_dv_create_flow_action_packet_reformat\n \t\t(ctx, data_sz, data, reformat_type, ft_type);\n \treturn action;\n #endif\n@@ -908,6 +989,18 @@ mlx5_glue_dv_destroy_flow(void *flow_id)\n #endif\n }\n \n+static int\n+__mlx5_glue_dv_destroy_flow_matcher(void *matcher)\n+{\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\treturn mlx5dv_destroy_flow_matcher(matcher);\n+#else\n+\t(void)matcher;\n+\terrno = ENOTSUP;\n+\treturn errno;\n+#endif\n+}\n+\n static int\n mlx5_glue_dv_destroy_flow_matcher(void *matcher)\n {\n@@ -915,7 +1008,7 @@ mlx5_glue_dv_destroy_flow_matcher(void *matcher)\n #ifdef HAVE_MLX5DV_DR\n \treturn mlx5dv_dr_matcher_destroy(matcher);\n #else\n-\treturn mlx5dv_destroy_flow_matcher(matcher);\n+\treturn __mlx5_glue_dv_destroy_flow_matcher(matcher);\n #endif\n #else\n \t(void)matcher;\n@@ -1164,12 +1257,18 @@ mlx5_glue_devx_port_query(struct ibv_context *ctx,\n \t\tinfo->vport_id = devx_port.vport;\n \t\tinfo->query_flags |= MLX5_PORT_QUERY_VPORT;\n \t}\n+\tif (devx_port.flags & MLX5DV_QUERY_PORT_ESW_OWNER_VHCA_ID) {\n+\t\tinfo->esw_owner_vhca_id = devx_port.esw_owner_vhca_id;\n+\t\tinfo->query_flags |= MLX5_PORT_QUERY_ESW_OWNER_VHCA_ID;\n+\t}\n #else\n #ifdef HAVE_MLX5DV_DR_DEVX_PORT\n \t/* The legacy DevX port query API is implemented (prior v35). */\n \tstruct mlx5dv_devx_port devx_port = {\n \t\t.comp_mask = MLX5DV_DEVX_PORT_VPORT |\n-\t\t\t MLX5DV_DEVX_PORT_MATCH_REG_C_0\n+\t\t\t MLX5DV_DEVX_PORT_MATCH_REG_C_0 |\n+\t\t\t MLX5DV_DEVX_PORT_VPORT_VHCA_ID |\n+\t\t\t MLX5DV_DEVX_PORT_ESW_OWNER_VHCA_ID\n \t};\n \n \terr = mlx5dv_query_devx_port(ctx, port_num, &devx_port);\n@@ -1464,6 +1563,7 @@ const struct mlx5_glue *mlx5_glue = &(const struct mlx5_glue) {\n \t.close_device = mlx5_glue_close_device,\n \t.query_device = mlx5_glue_query_device,\n \t.query_device_ex = mlx5_glue_query_device_ex,\n+\t.get_device_name = mlx5_glue_get_device_name,\n \t.query_rt_values_ex = mlx5_glue_query_rt_values_ex,\n \t.query_port = mlx5_glue_query_port,\n \t.create_comp_channel = mlx5_glue_create_comp_channel,\n@@ -1522,7 +1622,9 @@ const struct mlx5_glue *mlx5_glue = &(const struct mlx5_glue) {\n \t.dv_init_obj = mlx5_glue_dv_init_obj,\n \t.dv_create_qp = mlx5_glue_dv_create_qp,\n \t.dv_create_flow_matcher = mlx5_glue_dv_create_flow_matcher,\n+\t.dv_create_flow_matcher_root = __mlx5_glue_dv_create_flow_matcher,\n \t.dv_create_flow = mlx5_glue_dv_create_flow,\n+\t.dv_create_flow_root = __mlx5_glue_dv_create_flow,\n \t.dv_create_flow_action_counter =\n \t\tmlx5_glue_dv_create_flow_action_counter,\n \t.dv_create_flow_action_dest_ibv_qp =\n@@ -1531,8 +1633,12 @@ const struct mlx5_glue *mlx5_glue = &(const struct mlx5_glue) {\n \t\tmlx5_glue_dv_create_flow_action_dest_devx_tir,\n \t.dv_create_flow_action_modify_header =\n \t\tmlx5_glue_dv_create_flow_action_modify_header,\n+\t.dv_create_flow_action_modify_header_root =\n+\t\t__mlx5_glue_dv_create_flow_action_modify_header,\n \t.dv_create_flow_action_packet_reformat =\n \t\tmlx5_glue_dv_create_flow_action_packet_reformat,\n+\t.dv_create_flow_action_packet_reformat_root =\n+\t\t__mlx5_glue_dv_create_flow_action_packet_reformat,\n \t.dv_create_flow_action_tag = mlx5_glue_dv_create_flow_action_tag,\n \t.dv_create_flow_action_meter = mlx5_glue_dv_create_flow_action_meter,\n \t.dv_modify_flow_action_meter = mlx5_glue_dv_modify_flow_action_meter,\n@@ -1541,6 +1647,7 @@ const struct mlx5_glue *mlx5_glue = &(const struct mlx5_glue) {\n \t\tmlx5_glue_dr_create_flow_action_default_miss,\n \t.dv_destroy_flow = mlx5_glue_dv_destroy_flow,\n \t.dv_destroy_flow_matcher = mlx5_glue_dv_destroy_flow_matcher,\n+\t.dv_destroy_flow_matcher_root = __mlx5_glue_dv_destroy_flow_matcher,\n \t.dv_open_device = mlx5_glue_dv_open_device,\n \t.devx_obj_create = mlx5_glue_devx_obj_create,\n \t.devx_obj_destroy = mlx5_glue_devx_obj_destroy,\ndiff --git a/drivers/common/mlx5/linux/mlx5_glue.h b/drivers/common/mlx5/linux/mlx5_glue.h\nindex 9616dfdd06..88aa7430e8 100644\n--- a/drivers/common/mlx5/linux/mlx5_glue.h\n+++ b/drivers/common/mlx5/linux/mlx5_glue.h\n@@ -91,10 +91,12 @@ struct mlx5dv_port;\n \n #define MLX5_PORT_QUERY_VPORT (1u << 0)\n #define MLX5_PORT_QUERY_REG_C0 (1u << 1)\n+#define MLX5_PORT_QUERY_ESW_OWNER_VHCA_ID (1u << 2)\n \n struct mlx5_port_info {\n \tuint16_t query_flags;\n \tuint16_t vport_id; /* Associated VF vport index (if any). */\n+\tuint16_t esw_owner_vhca_id; /* Associated the esw_owner that this VF belongs to. */\n \tuint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */\n \tuint32_t vport_meta_mask; /* Used for vport index field match mask. */\n };\n@@ -164,6 +166,7 @@ struct mlx5_glue {\n \tint (*query_device_ex)(struct ibv_context *context,\n \t\t\t const struct ibv_query_device_ex_input *input,\n \t\t\t struct ibv_device_attr_ex *attr);\n+\tconst char *(*get_device_name)(struct ibv_device *device);\n \tint (*query_rt_values_ex)(struct ibv_context *context,\n \t\t\t struct ibv_values_ex *values);\n \tint (*query_port)(struct ibv_context *context, uint8_t port_num,\n@@ -268,8 +271,13 @@ struct mlx5_glue {\n \t\t(struct ibv_context *context,\n \t\t struct mlx5dv_flow_matcher_attr *matcher_attr,\n \t\t void *tbl);\n+\tvoid *(*dv_create_flow_matcher_root)\n+\t\t(struct ibv_context *context,\n+\t\t struct mlx5dv_flow_matcher_attr *matcher_attr);\n \tvoid *(*dv_create_flow)(void *matcher, void *match_value,\n \t\t\t size_t num_actions, void *actions[]);\n+\tvoid *(*dv_create_flow_root)(void *matcher, void *match_value,\n+\t\t\t\t size_t num_actions, void *actions);\n \tvoid *(*dv_create_flow_action_counter)(void *obj, uint32_t offset);\n \tvoid *(*dv_create_flow_action_dest_ibv_qp)(void *qp);\n \tvoid *(*dv_create_flow_action_dest_devx_tir)(void *tir);\n@@ -277,12 +285,20 @@ struct mlx5_glue {\n \t\t(struct ibv_context *ctx, enum mlx5dv_flow_table_type ft_type,\n \t\t void *domain, uint64_t flags, size_t actions_sz,\n \t\t uint64_t actions[]);\n+\tvoid *(*dv_create_flow_action_modify_header_root)\n+\t\t(struct ibv_context *ctx, size_t actions_sz, uint64_t actions[],\n+\t\t enum mlx5dv_flow_table_type ft_type);\n \tvoid *(*dv_create_flow_action_packet_reformat)\n \t\t(struct ibv_context *ctx,\n \t\t enum mlx5dv_flow_action_packet_reformat_type reformat_type,\n \t\t enum mlx5dv_flow_table_type ft_type,\n \t\t struct mlx5dv_dr_domain *domain,\n \t\t uint32_t flags, size_t data_sz, void *data);\n+\tvoid *(*dv_create_flow_action_packet_reformat_root)\n+\t\t(struct ibv_context *ctx,\n+\t\t size_t data_sz, void *data,\n+\t\t enum mlx5dv_flow_action_packet_reformat_type reformat_type,\n+\t\t enum mlx5dv_flow_table_type ft_type);\n \tvoid *(*dv_create_flow_action_tag)(uint32_t tag);\n \tvoid *(*dv_create_flow_action_meter)\n \t\t(struct mlx5dv_dr_flow_meter_attr *attr);\n@@ -291,6 +307,7 @@ struct mlx5_glue {\n \tvoid *(*dr_create_flow_action_default_miss)(void);\n \tint (*dv_destroy_flow)(void *flow);\n \tint (*dv_destroy_flow_matcher)(void *matcher);\n+\tint (*dv_destroy_flow_matcher_root)(void *matcher);\n \tstruct ibv_context *(*dv_open_device)(struct ibv_device *device);\n \tstruct mlx5dv_var *(*dv_alloc_var)(struct ibv_context *context,\n \t\t\t\t\t uint32_t flags);\n", "prefixes": [ "v6", "07/18" ] }