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GET /api/patches/118813/?format=api
{ "id": 118813, "url": "http://patches.dpdk.org/api/patches/118813/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221020155749.16643-6-valex@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221020155749.16643-6-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221020155749.16643-6-valex@nvidia.com", "date": "2022-10-20T15:57:35", "name": "[v6,05/18] common/mlx5: query set capability of registers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8099f81b6b600b29bdd131544dda5eadbe243022", "submitter": { "id": 2858, "url": "http://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221020155749.16643-6-valex@nvidia.com/mbox/", "series": [ { "id": 25345, "url": "http://patches.dpdk.org/api/series/25345/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25345", "date": "2022-10-20T15:57:30", "name": "net/mlx5: Add HW steering low level support", "version": 6, "mbox": "http://patches.dpdk.org/series/25345/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/118813/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/118813/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 372EEA0553;\n\tThu, 20 Oct 2022 17:59:43 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5E30842B84;\n\tThu, 20 Oct 2022 17:59:19 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2072.outbound.protection.outlook.com [40.107.223.72])\n by mails.dpdk.org (Postfix) with ESMTP id 5081542905\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=none (sender ip is\n 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=fail (p=reject sp=reject pct=100) action=oreject\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=P6YPqGsmLvUPm8AbOHwD51VmCPEC60NjyRHq+Fzx7o8=;\n b=ITI+7NYFFrCnwwN/5xwc6c16gEf/Og5hpUCG5tUp+Kk3tcXI6TSr7A+jNkWb4NX8GYRzsIrQfOZnfqwLk1fZJsBmY8Kcwz/islUzROjv099UpaOX5YQbNRtVbdu4XOHaU99cED0tuRWJZVYSKMfxXO/afDNyeGHI2rdzmoIdkZFIekZJ2N7XaFcCy67uvBdRE8fa1Mw9WoQVwBWfK/Hwl8i2LS3FQ8HxehIogmHIcCi0E72qF0IOUR1+EXnATlqrdAtYmAHmrMRIz2OJQeRz7tqGIzb//5Q9XXMYtEfEBgdaeq1LpyfCx39a6vTCEIndQxoWxZ/wCP2neWKHHIwlHA==", "X-MS-Exchange-Authentication-Results": "spf=none (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=fail action=oreject header.from=nvidia.com;", "Received-SPF": "None (protection.outlook.com: nvidia.com does not designate\n permitted sender hosts)", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, Bing Zhao <bingz@nvidia.com>", "Subject": "[v6 05/18] common/mlx5: query set capability of registers", "Date": "Thu, 20 Oct 2022 18:57:35 +0300", "Message-ID": "<20221020155749.16643-6-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221020155749.16643-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221020155749.16643-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT071:EE_|IA1PR12MB6068:EE_", "X-MS-Office365-Filtering-Correlation-Id": "7ef3623b-91a2-4963-548f-08dab2b40826", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n H64DhYBn0azpQtCW6XuLj4sQnQ0JhbCiCzDeq6xoj8oiR1yQd0h7RN+AqkZ7OKSeizK/Gz/hjEuHDjZSQ0GMdeuE4WFxzLWyBDGY8zRwQcuStIQH7V59DX9eto3CapWn7bRgHOdCTUi0zNeWzV9QqqIz1H23gvHPhR/t0p3toyv0Ksf9wbmbuDfoj06e8k4iUAqGc+dzBaar4v/7PXRl4jfgcB9oHwxPOsWgvY5c60gjY2+JH53jQCfOWvKosLPYVSaJvVX2zbmFQGyecacHYnx4EwL6DSidz9+wibZpbOwjJA0c7wOqZJlwUZ0cjzwREIajNeTJ2vgtphABgy7HzJH5zQCsp6jDFwcICsV3e47MPWDecgS3OSoqE+beqEM1Uj7JdxyH2mNcK0BNZ/54lnL5DAImv+v4Crl6gbg3pu55i8oWTGr9xt+8cqk0ZqN2LQ75UNdsEa8DWoS1KeIu5Y100RhoNgFHhb5DmswjUGcPrf2JBBvoUlmM4hi1L6jiHU/gQraxEngSKPkBUSYg3ai5V4DpyB5ARTy/gr1XHhdgcNuPI7vnu+TGuYhYO0FNS19idBdwOIlNo6WH7ZOFU0x7j4AzPxHZyoaxyjZ5d8zQN36tTReWh1S8DqgKNfHxeqSnleSPvNAcxoWo1l0xm21j6opqWsuu1l77IEkBvqxmMjQNJI1Flwpxk0vKFRcXqkAevVytPU47qQ/7cD+g0MNKGoIBDyR6tbJhg1v9hXwa7ObdXlfaMC+VpTw8DxaL5bp/wYcClH+B4QFa9kVavQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(39860400002)(396003)(376002)(346002)(136003)(451199015)(46966006)(36840700001)(40470700004)(336012)(186003)(1076003)(26005)(6666004)(6286002)(107886003)(426003)(47076005)(55016003)(7696005)(40460700003)(83380400001)(2906002)(16526019)(36860700001)(5660300002)(2616005)(40480700001)(478600001)(70586007)(110136005)(6636002)(316002)(70206006)(82310400005)(8676002)(41300700001)(4326008)(8936002)(54906003)(86362001)(36756003)(356005)(82740400003)(7636003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Oct 2022 15:59:12.4746 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7ef3623b-91a2-4963-548f-08dab2b40826", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT071.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB6068", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Bing Zhao <bingz@nvidia.com>\n\nIn the flow table capabilities, new fields are added to query the\ncapability to set, add, copy to a REG_C_x.\n\nThe set capability are queried and saved for the future usage.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 30 +++++++++++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++\n drivers/common/mlx5/mlx5_prm.h | 45 +++++++++++++++++++++++++---\n 3 files changed, 73 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 76f0b6724f..9c185366d0 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -1064,6 +1064,24 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->modify_outer_ip_ecn = MLX5_GET\n \t\t(flow_table_nic_cap, hcattr,\n \t\t ft_header_modify_nic_receive.outer_ip_ecn);\n+\tattr->set_reg_c = 0xff;\n+\tif (attr->nic_flow_table) {\n+#define GET_RX_REG_X_BITS \\\n+\t\tMLX5_GET(flow_table_nic_cap, hcattr, \\\n+\t\t\t ft_header_modify_nic_receive.metadata_reg_c_x)\n+#define GET_TX_REG_X_BITS \\\n+\t\tMLX5_GET(flow_table_nic_cap, hcattr, \\\n+\t\t\t ft_header_modify_nic_transmit.metadata_reg_c_x)\n+\n+\t\tuint32_t tx_reg, rx_reg;\n+\n+\t\ttx_reg = GET_TX_REG_X_BITS;\n+\t\trx_reg = GET_RX_REG_X_BITS;\n+\t\tattr->set_reg_c &= (rx_reg & tx_reg);\n+\n+#undef GET_RX_REG_X_BITS\n+#undef GET_TX_REG_X_BITS\n+\t}\n \tattr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);\n \tattr->inner_ipv4_ihl = MLX5_GET\n \t\t(flow_table_nic_cap, hcattr,\n@@ -1163,6 +1181,18 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\tattr->esw_mgr_vport_id =\n \t\t\tMLX5_GET(esw_cap, hcattr, esw_manager_vport_number);\n \t}\n+\tif (attr->eswitch_manager) {\n+\t\tuint32_t esw_reg;\n+\n+\t\thcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,\n+\t\t\t\tMLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE |\n+\t\t\t\tMLX5_HCA_CAP_OPMOD_GET_CUR);\n+\t\tif (!hcattr)\n+\t\t\treturn rc;\n+\t\tesw_reg = MLX5_GET(flow_table_esw_cap, hcattr,\n+\t\t\t\t ft_header_modify_esw_fdb.metadata_reg_c_x);\n+\t\tattr->set_reg_c &= esw_reg;\n+\t}\n \treturn 0;\n error:\n \trc = (rc > 0) ? -rc : rc;\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex cceaf3411d..a10aa3331b 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -263,6 +263,8 @@ struct mlx5_hca_attr {\n \tuint32_t crypto_wrapped_import_method:1;\n \tuint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */\n \tuint16_t max_wqe_sz_sq;\n+\tuint32_t set_reg_c:8;\n+\tuint32_t nic_flow_table:1;\n \tuint32_t modify_outer_ip_ecn:1;\n };\n \ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 9c1c93f916..ca4763f53d 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1295,6 +1295,7 @@ enum {\n \tMLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,\n+\tMLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE = 0x8 << 1,\n \tMLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_CRYPTO = 0x1A << 1,\n@@ -1892,6 +1893,7 @@ struct mlx5_ifc_roce_caps_bits {\n };\n \n struct mlx5_ifc_ft_fields_support_bits {\n+\t/* set_action_field_support */\n \tu8 outer_dmac[0x1];\n \tu8 outer_smac[0x1];\n \tu8 outer_ether_type[0x1];\n@@ -1919,7 +1921,7 @@ struct mlx5_ifc_ft_fields_support_bits {\n \tu8 outer_gre_key[0x1];\n \tu8 outer_vxlan_vni[0x1];\n \tu8 reserved_at_1a[0x5];\n-\tu8 source_eswitch_port[0x1];\n+\tu8 source_eswitch_port[0x1]; /* end of DW0 */\n \tu8 inner_dmac[0x1];\n \tu8 inner_smac[0x1];\n \tu8 inner_ether_type[0x1];\n@@ -1943,8 +1945,33 @@ struct mlx5_ifc_ft_fields_support_bits {\n \tu8 inner_tcp_sport[0x1];\n \tu8 inner_tcp_dport[0x1];\n \tu8 inner_tcp_flags[0x1];\n-\tu8 reserved_at_37[0x9];\n-\tu8 reserved_at_40[0x40];\n+\tu8 reserved_at_37[0x9]; /* end of DW1 */\n+\tu8 reserved_at_40[0x20]; /* end of DW2 */\n+\tu8 reserved_at_60[0x18];\n+\tunion {\n+\t\tstruct {\n+\t\t\tu8 metadata_reg_c_7[0x1];\n+\t\t\tu8 metadata_reg_c_6[0x1];\n+\t\t\tu8 metadata_reg_c_5[0x1];\n+\t\t\tu8 metadata_reg_c_4[0x1];\n+\t\t\tu8 metadata_reg_c_3[0x1];\n+\t\t\tu8 metadata_reg_c_2[0x1];\n+\t\t\tu8 metadata_reg_c_1[0x1];\n+\t\t\tu8 metadata_reg_c_0[0x1];\n+\t\t};\n+\t\tu8 metadata_reg_c_x[0x8];\n+\t}; /* end of DW3 */\n+\t/* set_action_field_support_2 */\n+\tu8 reserved_at_80[0x80];\n+\t/* add_action_field_support */\n+\tu8 reserved_at_100[0x80];\n+\t/* add_action_field_support_2 */\n+\tu8 reserved_at_180[0x80];\n+\t/* copy_action_field_support */\n+\tu8 reserved_at_200[0x80];\n+\t/* copy_action_field_support_2 */\n+\tu8 reserved_at_280[0x80];\n+\tu8 reserved_at_300[0x100];\n };\n \n /*\n@@ -1989,9 +2016,18 @@ struct mlx5_ifc_flow_table_nic_cap_bits {\n \tu8 reserved_at_e00[0x200];\n \tstruct mlx5_ifc_ft_fields_support_bits\n \t\tft_header_modify_nic_receive;\n-\tu8 reserved_at_1080[0x380];\n \tstruct mlx5_ifc_ft_fields_support_2_bits\n \t\tft_field_support_2_nic_receive;\n+\tu8 reserved_at_1480[0x780];\n+\tstruct mlx5_ifc_ft_fields_support_bits\n+\t\tft_header_modify_nic_transmit;\n+\tu8 reserved_at_2000[0x6000];\n+};\n+\n+struct mlx5_ifc_flow_table_esw_cap_bits {\n+\tu8 reserved_at_0[0x800];\n+\tstruct mlx5_ifc_ft_fields_support_bits ft_header_modify_esw_fdb;\n+\tu8 reserved_at_C00[0x7400];\n };\n \n /*\n@@ -2046,6 +2082,7 @@ union mlx5_ifc_hca_cap_union_bits {\n \tstruct mlx5_ifc_qos_cap_bits qos_cap;\n \tstruct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;\n \tstruct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;\n+\tstruct mlx5_ifc_flow_table_esw_cap_bits flow_table_esw_cap;\n \tstruct mlx5_ifc_esw_cap_bits esw_cap;\n \tstruct mlx5_ifc_roce_caps_bits roce_caps;\n \tu8 reserved_at_0[0x8000];\n", "prefixes": [ "v6", "05/18" ] }