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GET /api/patches/118809/?format=api
{ "id": 118809, "url": "http://patches.dpdk.org/api/patches/118809/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221020155749.16643-5-valex@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221020155749.16643-5-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221020155749.16643-5-valex@nvidia.com", "date": "2022-10-20T15:57:34", "name": "[v6,04/18] net/mlx5: add port to metadata conversion", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "dc40e1f4ee63451e7e57404a22540466b923b4a8", "submitter": { "id": 2858, "url": "http://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221020155749.16643-5-valex@nvidia.com/mbox/", "series": [ { "id": 25345, "url": "http://patches.dpdk.org/api/series/25345/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25345", "date": "2022-10-20T15:57:30", "name": "net/mlx5: Add HW steering low level support", "version": 6, "mbox": "http://patches.dpdk.org/series/25345/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/118809/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/118809/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 09BF9A0553;\n\tThu, 20 Oct 2022 17:59:12 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D2E5B4280E;\n\tThu, 20 Oct 2022 17:59:09 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2061.outbound.protection.outlook.com [40.107.244.61])\n by mails.dpdk.org (Postfix) with ESMTP id 89B8441614\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=none (sender ip is\n 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=fail (p=reject sp=reject pct=100) action=oreject\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=Dw3vZJpV15VCYI4asQ68u4xh1oEtxo19932fcBD5Ums=;\n b=snJbDmiY3UaTapXxAkWRT3Lvnit1a5WKnG7oCcKxO6a5sPI0MLTLjdThwomEk3rYM4Z1FPsgKSXmXqQUgQQSgxOiT396NXJ7+zoD7xi8bX41O8Bh49Kit9ESGymNL24nAXw8MzmFX0o+pv6hkygrsT2SA3QW9HW5+ykHGC+WwffG4axZtHa3BzON+N7levs94xBGODkChej6fRszK+sRx6m54n90Kn6msxBSdYwQfz3WiohuRGJViTekj7dAYrzL1JN0dHIqKXJlifU54LjJYGdYT8uK99ygzphXXjGL8Mlsnq3bRXydIjbBsp+6RZGH3eCUJtDjRroBbd/LaawGmg==", "X-MS-Exchange-Authentication-Results": "spf=none (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=fail action=oreject header.from=nvidia.com;", "Received-SPF": "None (protection.outlook.com: nvidia.com does not designate\n permitted sender hosts)", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, Dariusz Sosnowski\n <dsosnowski@nvidia.com>", "Subject": "[v6 04/18] net/mlx5: add port to metadata conversion", "Date": "Thu, 20 Oct 2022 18:57:34 +0300", "Message-ID": "<20221020155749.16643-5-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221020155749.16643-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221020155749.16643-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT097:EE_|PH7PR12MB7380:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6e5bebc8-392e-47c6-3739-08dab2b40461", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n M7KxjO6k3y3KCSiyBrFcWKy+gsccSOJsWPxeOeUY4/81jRbQMzwMoZiTYpCriZDw2/hbO3jgieIxVOiqXXsYRZ+aLB1yNERhVvwWgs5iElVTfkrlJLSVKLjhEFJJ58ozxgZZiaCMk4MYIYeckFPWtjN+crCRJnDBTamAzLgULF30QDpNLHnNUevtsMRX4+YhDAlCcGu2fU1u/8NKy5j3e7NJfosIShMPM4abNl2gl2tsQU853IWFyGx1wXP3cQJYXXxkZD1SZD7Q8Ricx5b9k5N9sdpHZxU6vGH9Oo9GZjBhrqCCjWGX2FBJz0JOOjupsyjd8oVt+t3fbnm1H7/V9v6PAPlBd+y63UgCX76v3hE5BHBKcuYjB1Gf6O8wNTTTMY3EGfb6wRS/cJDFeBspNb+3Ggu3/YJvoRq9Jed8rjBvu/9vuidPDKOjED++9E011Bno95xSdrCHH1OeVWbk+P5DNOGw0mPGqllb/VggXZOeAqjTPdD5NnELegPrbKUV93duILEyXfe5cTK4TM6LnglXhbH0mMz1rACVHu8K/Eqw3JVdfEDe8l+UY5kL4OA/zLi+oHOixi2zQACr1qzB5YMS/PFzLYDG7Kpk6aYUrfX3LBNY/edQItUyupdo7H1G7wnJnEBITNMGjBwmuBnr1UfVSRfVz323YiKRASyzXj5RtxGlsjUar/La0xsK01uf1Y1UY9Z0M87awKXKeZ2j3QHb5w4P5CLXAtd1U6qHGq3iCLscZ+VMfAi4HvIwaUrnQSh+tAKshHH07UxuVdiYWjcAQYmS+pwEAfD9sDmSf0JFXlZBHhLEqGBM/iXeSMQd", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(396003)(39860400002)(376002)(346002)(136003)(451199015)(46966006)(36840700001)(40470700004)(82310400005)(7636003)(36756003)(2616005)(478600001)(5660300002)(356005)(83380400001)(70206006)(6666004)(107886003)(47076005)(70586007)(4326008)(8676002)(55016003)(8936002)(41300700001)(7696005)(6286002)(86362001)(36860700001)(336012)(54906003)(6636002)(426003)(26005)(110136005)(16526019)(40460700003)(40480700001)(316002)(1076003)(186003)(2906002)(82740400003)(21314003)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Oct 2022 15:59:06.2277 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6e5bebc8-392e-47c6-3739-08dab2b40461", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT097.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB7380", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Dariusz Sosnowski <dsosnowski@nvidia.com>\n\nThis patch initial version of functions used to:\n\n- convert between ethdev port_id and internal tag/mask value,\n- convert between IB context and internal tag/mask value.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 10 +++++-\n drivers/net/mlx5/mlx5.c | 1 +\n drivers/net/mlx5/mlx5_flow.c | 6 ++++\n drivers/net/mlx5/mlx5_flow.h | 52 ++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow_hw.c | 29 ++++++++++++++++++\n 5 files changed, 97 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 3e505d8f4c..d1e7bcce57 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1554,8 +1554,16 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tif (!priv->hrxqs)\n \t\tgoto error;\n \trte_rwlock_init(&priv->ind_tbls_lock);\n-\tif (priv->sh->config.dv_flow_en == 2)\n+\tif (priv->sh->config.dv_flow_en == 2) {\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\t\tif (priv->vport_meta_mask)\n+\t\t\tflow_hw_set_port_info(eth_dev);\n \t\treturn eth_dev;\n+#else\n+\t\tDRV_LOG(ERR, \"DV support is missing for HWS.\");\n+\t\tgoto error;\n+#endif\n+\t}\n \t/* Port representor shares the same max priority with pf port. */\n \tif (!priv->sh->flow_priority_check_flag) {\n \t\t/* Supported Verbs flow priority number detection. */\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 752b60d769..1d10932619 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1944,6 +1944,7 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n \tmlx5_flex_item_port_cleanup(dev);\n #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \tflow_hw_resource_release(dev);\n+\tflow_hw_clear_port_info(dev);\n #endif\n \tif (priv->rxq_privs != NULL) {\n \t\t/* XXX race condition if mlx5_rx_burst() is still running. */\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 026d77b01f..72f4374c07 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -33,6 +33,12 @@\n #include \"mlx5_common_os.h\"\n #include \"rte_pmd_mlx5.h\"\n \n+/*\n+ * Shared array for quick translation between port_id and vport mask/values\n+ * used for HWS rules.\n+ */\n+struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS];\n+\n struct tunnel_default_miss_ctx {\n \tuint16_t *queue;\n \t__extension__\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 3537eb3d66..c0c719dd8b 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1326,6 +1326,58 @@ struct mlx5_flow_split_info {\n \tuint64_t prefix_layers; /**< Prefix subflow layers. */\n };\n \n+struct flow_hw_port_info {\n+\tuint32_t regc_mask;\n+\tuint32_t regc_value;\n+\tuint32_t is_wire:1;\n+};\n+\n+extern struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS];\n+\n+/*\n+ * Get metadata match tag and mask for given rte_eth_dev port.\n+ * Used in HWS rule creation.\n+ */\n+static __rte_always_inline const struct flow_hw_port_info *\n+flow_hw_conv_port_id(const uint16_t port_id)\n+{\n+\tstruct flow_hw_port_info *port_info;\n+\n+\tif (port_id >= RTE_MAX_ETHPORTS)\n+\t\treturn NULL;\n+\tport_info = &mlx5_flow_hw_port_infos[port_id];\n+\treturn !!port_info->regc_mask ? port_info : NULL;\n+}\n+\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+/*\n+ * Get metadata match tag and mask for the uplink port represented\n+ * by given IB context. Used in HWS context creation.\n+ */\n+static __rte_always_inline const struct flow_hw_port_info *\n+flow_hw_get_wire_port(struct ibv_context *ibctx)\n+{\n+\tstruct ibv_device *ibdev = ibctx->device;\n+\tuint16_t port_id;\n+\n+\tMLX5_ETH_FOREACH_DEV(port_id, NULL) {\n+\t\tconst struct mlx5_priv *priv =\n+\t\t\t\trte_eth_devices[port_id].data->dev_private;\n+\n+\t\tif (priv && priv->master) {\n+\t\t\tstruct ibv_context *port_ibctx = priv->sh->cdev->ctx;\n+\n+\t\t\tif (port_ibctx->device == ibdev)\n+\t\t\t\treturn flow_hw_conv_port_id(port_id);\n+\t\t}\n+\t}\n+\treturn NULL;\n+}\n+#endif\n+\n+void flow_hw_set_port_info(struct rte_eth_dev *dev);\n+void flow_hw_clear_port_info(struct rte_eth_dev *dev);\n+\n typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,\n \t\t\t\t const struct rte_flow_attr *attr,\n \t\t\t\t const struct rte_flow_item items[],\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex b168ff9e7e..765e5164cb 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -2211,6 +2211,35 @@ flow_hw_resource_release(struct rte_eth_dev *dev)\n \tpriv->nb_queue = 0;\n }\n \n+/* Sets vport tag and mask, for given port, used in HWS rules. */\n+void\n+flow_hw_set_port_info(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tuint16_t port_id = dev->data->port_id;\n+\tstruct flow_hw_port_info *info;\n+\n+\tMLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);\n+\tinfo = &mlx5_flow_hw_port_infos[port_id];\n+\tinfo->regc_mask = priv->vport_meta_mask;\n+\tinfo->regc_value = priv->vport_meta_tag;\n+\tinfo->is_wire = priv->master;\n+}\n+\n+/* Clears vport tag and mask used for HWS rules. */\n+void\n+flow_hw_clear_port_info(struct rte_eth_dev *dev)\n+{\n+\tuint16_t port_id = dev->data->port_id;\n+\tstruct flow_hw_port_info *info;\n+\n+\tMLX5_ASSERT(port_id < RTE_MAX_ETHPORTS);\n+\tinfo = &mlx5_flow_hw_port_infos[port_id];\n+\tinfo->regc_mask = 0;\n+\tinfo->regc_value = 0;\n+\tinfo->is_wire = 0;\n+}\n+\n /**\n * Create shared action.\n *\n", "prefixes": [ "v6", "04/18" ] }