Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/117914/?format=api
{ "id": 117914, "url": "http://patches.dpdk.org/api/patches/117914/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221011120135.45846-7-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221011120135.45846-7-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221011120135.45846-7-ndabilpuram@marvell.com", "date": "2022-10-11T12:01:29", "name": "[07/13] common/cnxk: sync NIX HW info mbox structure with kernel", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "112db24fc9aba95d04a2307a8d4be36583ced04b", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221011120135.45846-7-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 25145, "url": "http://patches.dpdk.org/api/series/25145/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25145", "date": "2022-10-11T12:01:23", "name": "[01/13] common/cnxk: set MTU size on SDP based on SoC type", "version": 1, "mbox": "http://patches.dpdk.org/series/25145/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/117914/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/117914/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 19AE3A0545;\n\tTue, 11 Oct 2022 14:02:24 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D7A0F42DD6;\n\tTue, 11 Oct 2022 14:02:01 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 6435E42DCB\n for <dev@dpdk.org>; Tue, 11 Oct 2022 14:02:00 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 29B9eR9N008930\n for <dev@dpdk.org>; Tue, 11 Oct 2022 05:01:59 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k40g4y29d-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 11 Oct 2022 05:01:59 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 11 Oct 2022 05:01:57 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 11 Oct 2022 05:01:57 -0700", "from localhost.localdomain (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 043AB3F705A;\n Tue, 11 Oct 2022 05:01:54 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=wvPBjEVmfOolP+4jc4k2ExGqK8p3vTvVE2hJukCWBcE=;\n b=iwo9NIY8AGK0G3falW4vZciJWTQFtEx2OgyM2vzynnOhs1eN+fONwyyk5lOWImhbKXfz\n yNUY4BnpGutd8/YhwY6bDXQd/309afMw8DTTzreRxmU0LQ8nR1Ci1vZqxybs5LrKFS4F\n sFKvDFKnCuzNH4qmdJmbOvXJ+DFwcksY278PxeTar2IMHpW4p2qwWX91+kXkoz6G/aAB\n JGEoYmSNzSIdxntWReertkB6E5+MniQohO/h9vN4I5tStGKMJPwQuQ6yWvmMq+421dvQ\n AoV1RVZIhvOU0g7MmgsgZB2K+Oi93cxbSqFnV+mxLmD8t3Y9/fvANV2PJlDF9OBN1opa WQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 07/13] common/cnxk: sync NIX HW info mbox structure with\n kernel", "Date": "Tue, 11 Oct 2022 17:31:29 +0530", "Message-ID": "<20221011120135.45846-7-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221011120135.45846-1-ndabilpuram@marvell.com>", "References": "<20221011120135.45846-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "GM2YjiS-U_cmXRjyA_eHh3tPwCs9FikU", "X-Proofpoint-GUID": "GM2YjiS-U_cmXRjyA_eHh3tPwCs9FikU", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Satha Rao <skoteshwar@marvell.com>\n\nSync nix_hw_info structure with kernel.\n\nMaintain default RR_QUANTUM for VF TL2 same as kernel to make\nequal distribution among all VFs.\n\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\n---\n drivers/common/cnxk/roc_mbox.h | 8 +++++-\n drivers/common/cnxk/roc_nix.c | 9 ++++++-\n drivers/common/cnxk/roc_nix.h | 1 +\n drivers/common/cnxk/roc_nix_tm.c | 10 ++++----\n drivers/common/cnxk/roc_nix_tm_utils.c | 34 +++++++++++++++++++++-----\n 5 files changed, 49 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex a47e6a8f3b..e8d4ae283d 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -1215,7 +1215,13 @@ struct nix_inline_ipsec_lf_cfg {\n struct nix_hw_info {\n \tstruct mbox_msghdr hdr;\n \tuint16_t __io vwqe_delay;\n-\tuint16_t __io rsvd[15];\n+\tuint16_t __io max_mtu;\n+\tuint16_t __io min_mtu;\n+\tuint32_t __io rpm_dwrr_mtu;\n+\tuint32_t __io sdp_dwrr_mtu;\n+\tuint32_t __io lbk_dwrr_mtu;\n+\tuint32_t __io rsvd32[1];\n+\tuint64_t __io rsvd[15]; /* Add reserved fields for future expansion */\n };\n \n struct nix_bandprof_alloc_req {\ndiff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c\nindex 8fd8ec8461..2a320cc291 100644\n--- a/drivers/common/cnxk/roc_nix.c\n+++ b/drivers/common/cnxk/roc_nix.c\n@@ -303,8 +303,15 @@ roc_nix_get_hw_info(struct roc_nix *roc_nix)\n \n \tmbox_alloc_msg_nix_get_hw_info(mbox);\n \trc = mbox_process_msg(mbox, (void *)&hw_info);\n-\tif (rc == 0)\n+\tif (rc == 0) {\n \t\tnix->vwqe_interval = hw_info->vwqe_delay;\n+\t\tif (nix->lbk_link)\n+\t\t\troc_nix->dwrr_mtu = hw_info->lbk_dwrr_mtu;\n+\t\telse if (nix->sdp_link)\n+\t\t\troc_nix->dwrr_mtu = hw_info->sdp_dwrr_mtu;\n+\t\telse\n+\t\t\troc_nix->dwrr_mtu = hw_info->rpm_dwrr_mtu;\n+\t}\n \n \treturn rc;\n }\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 5c2a869eba..1eb1c9af55 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -422,6 +422,7 @@ struct roc_nix {\n \tuint32_t ipsec_in_min_spi;\n \tuint32_t ipsec_in_max_spi;\n \tuint32_t ipsec_out_max_sa;\n+\tuint32_t dwrr_mtu;\n \tbool ipsec_out_sso_pffunc;\n \tbool custom_sa_action;\n \t/* End of input parameters */\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex 81fa6b1d93..86918990a2 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -256,10 +256,6 @@ nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node)\n \tif (node->weight > roc_nix_tm_max_sched_wt_get())\n \t\treturn NIX_ERR_TM_WEIGHT_EXCEED;\n \n-\t/* Maintain minimum weight */\n-\tif (!node->weight)\n-\t\tnode->weight = 1;\n-\n \tnode->hw_lvl = nix_tm_lvl2nix(nix, lvl);\n \tnode->rr_prio = 0xF;\n \tnode->max_prio = UINT32_MAX;\n@@ -1358,7 +1354,11 @@ nix_tm_prepare_default_tree(struct roc_nix *roc_nix)\n \t\tnode->id = nonleaf_id;\n \t\tnode->parent_id = parent;\n \t\tnode->priority = 0;\n-\t\tnode->weight = NIX_TM_DFLT_RR_WT;\n+\t\t/* Default VF root RR_QUANTUM is in sync with kernel */\n+\t\tif (lvl == ROC_TM_LVL_ROOT && !nix_tm_have_tl1_access(nix))\n+\t\t\tnode->weight = 0;\n+\t\telse\n+\t\t\tnode->weight = NIX_TM_DFLT_RR_WT;\n \t\tnode->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;\n \t\tnode->lvl = lvl;\n \t\tnode->tree = ROC_NIX_TM_DEFAULT;\ndiff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c\nindex 193f9df5ff..d33e793664 100644\n--- a/drivers/common/cnxk/roc_nix_tm_utils.c\n+++ b/drivers/common/cnxk/roc_nix_tm_utils.c\n@@ -644,9 +644,25 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,\n \treturn k;\n }\n \n+static inline int\n+nix_tm_default_rr_weight(struct nix *nix)\n+{\n+\tstruct roc_nix *roc_nix = nix_priv_to_roc_nix(nix);\n+\tuint32_t max_pktlen = roc_nix_max_pkt_len(roc_nix);\n+\tuint32_t weight;\n+\n+\t/* Reduce TX VTAG Insertions */\n+\tmax_pktlen -= 8;\n+\tweight = max_pktlen / roc_nix->dwrr_mtu;\n+\tif (max_pktlen % roc_nix->dwrr_mtu)\n+\t\tweight += 1;\n+\n+\treturn weight;\n+}\n+\n uint8_t\n-nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node,\n-\t\t volatile uint64_t *reg, volatile uint64_t *regval)\n+nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node, volatile uint64_t *reg,\n+\t\t volatile uint64_t *regval)\n {\n \tuint64_t strict_prio = node->priority;\n \tuint32_t hw_lvl = node->hw_lvl;\n@@ -654,8 +670,14 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node,\n \tuint64_t rr_quantum;\n \tuint8_t k = 0;\n \n-\t/* For CN9K, weight needs to be converted to quantum */\n-\trr_quantum = nix_tm_weight_to_rr_quantum(node->weight);\n+\t/* If minimum weight not provided, then by default RR_QUANTUM\n+\t * should be in sync with kernel, i.e., single MTU value\n+\t */\n+\tif (!node->weight)\n+\t\trr_quantum = nix_tm_default_rr_weight(nix);\n+\telse\n+\t\t/* For CN9K, weight needs to be converted to quantum */\n+\t\trr_quantum = nix_tm_weight_to_rr_quantum(node->weight);\n \n \t/* For children to root, strict prio is default if either\n \t * device root is TL2 or TL1 Static Priority is disabled.\n@@ -666,8 +688,8 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node,\n \n \tplt_tm_dbg(\"Schedule config node %s(%u) lvl %u id %u, \"\n \t\t \"prio 0x%\" PRIx64 \", rr_quantum/rr_wt 0x%\" PRIx64 \" (%p)\",\n-\t\t nix_tm_hwlvl2str(node->hw_lvl), schq, node->lvl, node->id,\n-\t\t strict_prio, rr_quantum, node);\n+\t\t nix_tm_hwlvl2str(node->hw_lvl), schq, node->lvl, node->id, strict_prio,\n+\t\t rr_quantum, node);\n \n \tswitch (hw_lvl) {\n \tcase NIX_TXSCH_LVL_SMQ:\n", "prefixes": [ "07/13" ] }