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GET /api/patches/117912/?format=api
{ "id": 117912, "url": "http://patches.dpdk.org/api/patches/117912/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221011120135.45846-5-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221011120135.45846-5-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221011120135.45846-5-ndabilpuram@marvell.com", "date": "2022-10-11T12:01:27", "name": "[05/13] common/cnxk: fix RQ mask config for cn10kb chip", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "6b1eaabff425e56273ee2306817464a4bba18ef2", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221011120135.45846-5-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 25145, "url": "http://patches.dpdk.org/api/series/25145/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25145", "date": "2022-10-11T12:01:23", "name": "[01/13] common/cnxk: set MTU size on SDP based on SoC type", "version": 1, "mbox": "http://patches.dpdk.org/series/25145/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/117912/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/117912/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 43FEAA0545;\n\tTue, 11 Oct 2022 14:02:08 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 92EA142DC6;\n\tTue, 11 Oct 2022 14:01:56 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id CC1A142DC0\n for <dev@dpdk.org>; Tue, 11 Oct 2022 14:01:54 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 29B8OQA3030232\n for <dev@dpdk.org>; Tue, 11 Oct 2022 05:01:54 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3k54xugq6f-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 11 Oct 2022 05:01:53 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 11 Oct 2022 05:01:51 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 11 Oct 2022 05:01:51 -0700", "from localhost.localdomain (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id E5C423F7040;\n Tue, 11 Oct 2022 05:01:49 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=Zsc24S5RVFmtiGdiLW0SE77B+10vXl3e7NZnG11bTV0=;\n b=C7j26cipjog7qIEi/y31RKa72Dq7nwCZ7yGmEz12bmcQi5wFNtCqENM4x+yJdQtPkD4E\n VCOOx/A4cG5x0I3DaTvpBicFmBZfD0e5XQKmsAsg5OfOE5my3jJ30IWhdiMhTC8moRXx\n uLqOU0wB13regr1bLrHLsFc6+EwwMk+2Gl/wXsZxZmjUKmDf7tFSBMDg/I75DVLXTTVg\n DpNpJdADs+i35m9vKi+iNG/7XO0NiYpoEd4MACU8BmfD+4Io5lJYclKHXCzbFSZq3uOX\n /0v54rLXdhq9u5ghHBL4U2zgx6K7BWkCU/GIa1B5nu7WY1flKUWmRbraL8oYHPZAFCFi Qw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 05/13] common/cnxk: fix RQ mask config for cn10kb chip", "Date": "Tue, 11 Oct 2022 17:31:27 +0530", "Message-ID": "<20221011120135.45846-5-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221011120135.45846-1-ndabilpuram@marvell.com>", "References": "<20221011120135.45846-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "bDaevpgWDF9ZPDhjUFdT2b9kMSwkI945", "X-Proofpoint-ORIG-GUID": "bDaevpgWDF9ZPDhjUFdT2b9kMSwkI945", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "RQ mask config needs to enable SPB_ENA in order for Zero for\nbeing able to override it with Meta aura.\n\nAlso fix flow control config to catch invalid rxchan config\nerrors.\n\nFixes: ddf955d3917e (\"common/cnxk: support CPT second pass\")\nFixes: da57d4589a6f (\"common/cnxk: support NIX flow control\")\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix_fc.c | 4 ++-\n drivers/common/cnxk/roc_nix_inl.c | 43 +++++++++++++++++--------------\n 2 files changed, 26 insertions(+), 21 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex f4cfa11c0f..033e17a4bf 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -52,8 +52,10 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)\n \t\treq->bpid_per_chan = true;\n \n \t\trc = mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc || (req->chan_cnt != rsp->chan_cnt))\n+\t\tif (rc || (req->chan_cnt != rsp->chan_cnt)) {\n+\t\t\trc = -EIO;\n \t\t\tgoto exit;\n+\t\t}\n \n \t\tnix->chan_cnt = rsp->chan_cnt;\n \t\tfor (i = 0; i < rsp->chan_cnt; i++)\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex 213d71e684..0da097c9e9 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -454,27 +454,29 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)\n \tmsk_req->rq_set.lpb_drop_ena = 0;\n \tmsk_req->rq_set.spb_drop_ena = 0;\n \tmsk_req->rq_set.xqe_drop_ena = 0;\n+\tmsk_req->rq_set.spb_ena = 1;\n \n-\tmsk_req->rq_mask.len_ol3_dis = ~(msk_req->rq_set.len_ol3_dis);\n-\tmsk_req->rq_mask.len_ol4_dis = ~(msk_req->rq_set.len_ol4_dis);\n-\tmsk_req->rq_mask.len_il3_dis = ~(msk_req->rq_set.len_il3_dis);\n+\tmsk_req->rq_mask.len_ol3_dis = 0;\n+\tmsk_req->rq_mask.len_ol4_dis = 0;\n+\tmsk_req->rq_mask.len_il3_dis = 0;\n \n-\tmsk_req->rq_mask.len_il4_dis = ~(msk_req->rq_set.len_il4_dis);\n-\tmsk_req->rq_mask.csum_ol4_dis = ~(msk_req->rq_set.csum_ol4_dis);\n-\tmsk_req->rq_mask.csum_il4_dis = ~(msk_req->rq_set.csum_il4_dis);\n+\tmsk_req->rq_mask.len_il4_dis = 0;\n+\tmsk_req->rq_mask.csum_ol4_dis = 0;\n+\tmsk_req->rq_mask.csum_il4_dis = 0;\n \n-\tmsk_req->rq_mask.lenerr_dis = ~(msk_req->rq_set.lenerr_dis);\n-\tmsk_req->rq_mask.port_ol4_dis = ~(msk_req->rq_set.port_ol4_dis);\n-\tmsk_req->rq_mask.port_il4_dis = ~(msk_req->rq_set.port_il4_dis);\n+\tmsk_req->rq_mask.lenerr_dis = 0;\n+\tmsk_req->rq_mask.port_ol4_dis = 0;\n+\tmsk_req->rq_mask.port_il4_dis = 0;\n \n-\tmsk_req->rq_mask.lpb_drop_ena = ~(msk_req->rq_set.lpb_drop_ena);\n-\tmsk_req->rq_mask.spb_drop_ena = ~(msk_req->rq_set.spb_drop_ena);\n-\tmsk_req->rq_mask.xqe_drop_ena = ~(msk_req->rq_set.xqe_drop_ena);\n+\tmsk_req->rq_mask.lpb_drop_ena = 0;\n+\tmsk_req->rq_mask.spb_drop_ena = 0;\n+\tmsk_req->rq_mask.xqe_drop_ena = 0;\n+\tmsk_req->rq_mask.spb_ena = 0;\n \n \taura_handle = roc_npa_zero_aura_handle();\n \tmsk_req->ipsec_cfg1.spb_cpt_aura = roc_npa_aura_handle_to_aura(aura_handle);\n \tmsk_req->ipsec_cfg1.rq_mask_enable = enable;\n-\tmsk_req->ipsec_cfg1.spb_cpt_sizem1 = inl_cfg->buf_sz;\n+\tmsk_req->ipsec_cfg1.spb_cpt_sizem1 = (inl_cfg->buf_sz >> 7) - 1;\n \tmsk_req->ipsec_cfg1.spb_cpt_enable = enable;\n \n \treturn mbox_process(mbox);\n@@ -544,13 +546,6 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n \t\tidev->inl_cfg.refs++;\n \t}\n \n-\tif (roc_model_is_cn10kb_a0()) {\n-\t\trc = nix_inl_rq_mask_cfg(roc_nix, true);\n-\t\tif (rc) {\n-\t\t\tplt_err(\"Failed to get rq mask rc=%d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t}\n \tnix->inl_inb_ena = true;\n \treturn 0;\n }\n@@ -1043,6 +1038,14 @@ roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool enable)\n \tif (!idev)\n \t\treturn -EFAULT;\n \n+\tif (roc_model_is_cn10kb_a0()) {\n+\t\trc = nix_inl_rq_mask_cfg(roc_nix, true);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to get rq mask rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t}\n+\n \tif (nix->inb_inl_dev) {\n \t\tif (!inl_rq || !idev->nix_inl_dev)\n \t\t\treturn -EFAULT;\n", "prefixes": [ "05/13" ] }