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GET /api/patches/117647/?format=api
{ "id": 117647, "url": "http://patches.dpdk.org/api/patches/117647/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221007213851.31524-2-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221007213851.31524-2-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221007213851.31524-2-nicolas.chautru@intel.com", "date": "2022-10-07T21:38:38", "name": "[v9,01/14] baseband/acc100: remove unused registers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c9cc0eef909100eab2b39f886dc407edaca3d137", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221007213851.31524-2-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 25041, "url": "http://patches.dpdk.org/api/series/25041/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25041", "date": "2022-10-07T21:38:37", "name": "bbdev ACC200 PMD", "version": 9, "mbox": "http://patches.dpdk.org/series/25041/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/117647/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/117647/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 96F77A0543;\n\tFri, 7 Oct 2022 23:39:14 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5092242685;\n\tFri, 7 Oct 2022 23:39:10 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 4E7D240042\n for <dev@dpdk.org>; Fri, 7 Oct 2022 23:39:08 +0200 (CEST)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 07 Oct 2022 14:39:07 -0700", "from unknown (HELO icx-npg-scs1-cp1.localdomain) ([10.233.180.245])\n by orsmga007.jf.intel.com with ESMTP; 07 Oct 2022 14:39:06 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1665178748; x=1696714748;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=F70/TVLBxhTnr6qxYNXDjr4SN+WWV7otTCdd6s1qQVI=;\n b=nXFT03PhHloB/VrpKjZ7a5P87kEAmr5qJR2qrSPgnJYKocsRqC3xuwYE\n veMgo3bEOgMdUuG8Wdxq+bdnM0gYEGTYB67QrPCYU9yKERx6SzcOcRXHu\n lC9yvOhm0Fxzdpn1V73HXLHBjz8LDuZCgnaohu+/jcnlQgFVNYwz2IWqq\n tE12o7YwPdROBB2oVXrZA4GM9nIKajrIkXPoV6tjFwi2N+BF2+u810kLj\n IRsLyWncd5Q4//7PjqJ/gKMhwaJfItLYuI5lQxnF5BzP3u3OBHikAl5Oc\n y6Lgav9nyxpQntY2DIdxMw+DMobuCYdCmldERecgK9cHKsdc4WxxOhWME w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10493\"; a=\"291118494\"", "E=Sophos;i=\"5.95,167,1661842800\"; d=\"scan'208\";a=\"291118494\"", "E=McAfee;i=\"6500,9779,10493\"; a=\"620388432\"", "E=Sophos;i=\"5.95,167,1661842800\"; d=\"scan'208\";a=\"620388432\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tgakhil@marvell.com,\n\tmaxime.coquelin@redhat.com", "Cc": "trix@redhat.com, mdr@ashroe.eu, bruce.richardson@intel.com,\n hemant.agrawal@nxp.com, david.marchand@redhat.com,\n stephen@networkplumber.org, hernan.vargas@intel.com,\n Nic Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v9 01/14] baseband/acc100: remove unused registers", "Date": "Fri, 7 Oct 2022 14:38:38 -0700", "Message-Id": "<20221007213851.31524-2-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20221007213851.31524-1-nicolas.chautru@intel.com>", "References": "<20221007213851.31524-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Nic Chautru <nicolas.chautru@intel.com>\n\nCleanep up the enum files to remove un-used registers definitions.\nNo functionality change.\n\nSigned-off-by: Nic Chautru <nicolas.chautru@intel.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n drivers/baseband/acc100/acc100_pf_enum.h | 939 -----------------------\n 1 file changed, 939 deletions(-)", "diff": "diff --git a/drivers/baseband/acc100/acc100_pf_enum.h b/drivers/baseband/acc100/acc100_pf_enum.h\nindex 2fba667627..f4e5002762 100644\n--- a/drivers/baseband/acc100/acc100_pf_enum.h\n+++ b/drivers/baseband/acc100/acc100_pf_enum.h\n@@ -14,32 +14,6 @@\n enum {\n \tHWPfQmgrEgressQueuesTemplate = 0x0007FE00,\n \tHWPfQmgrIngressAq = 0x00080000,\n-\tHWPfQmgrArbQAvail = 0x00A00010,\n-\tHWPfQmgrArbQBlock = 0x00A00014,\n-\tHWPfQmgrAqueueDropNotifEn = 0x00A00024,\n-\tHWPfQmgrAqueueDisableNotifEn = 0x00A00028,\n-\tHWPfQmgrSoftReset = 0x00A00038,\n-\tHWPfQmgrInitStatus = 0x00A0003C,\n-\tHWPfQmgrAramWatchdogCount = 0x00A00040,\n-\tHWPfQmgrAramWatchdogCounterEn = 0x00A00044,\n-\tHWPfQmgrAxiWatchdogCount = 0x00A00048,\n-\tHWPfQmgrAxiWatchdogCounterEn = 0x00A0004C,\n-\tHWPfQmgrProcessWatchdogCount = 0x00A00050,\n-\tHWPfQmgrProcessWatchdogCounterEn = 0x00A00054,\n-\tHWPfQmgrProcessUl4GWatchdogCounter = 0x00A00058,\n-\tHWPfQmgrProcessDl4GWatchdogCounter = 0x00A0005C,\n-\tHWPfQmgrProcessUl5GWatchdogCounter = 0x00A00060,\n-\tHWPfQmgrProcessDl5GWatchdogCounter = 0x00A00064,\n-\tHWPfQmgrProcessMldWatchdogCounter = 0x00A00068,\n-\tHWPfQmgrMsiOverflowUpperVf = 0x00A00070,\n-\tHWPfQmgrMsiOverflowLowerVf = 0x00A00074,\n-\tHWPfQmgrMsiWatchdogOverflow = 0x00A00078,\n-\tHWPfQmgrMsiOverflowEnable = 0x00A0007C,\n-\tHWPfQmgrDebugAqPointerMemGrp = 0x00A00100,\n-\tHWPfQmgrDebugOutputArbQFifoGrp = 0x00A00140,\n-\tHWPfQmgrDebugMsiFifoGrp = 0x00A00180,\n-\tHWPfQmgrDebugAxiWdTimeoutMsiFifo = 0x00A001C0,\n-\tHWPfQmgrDebugProcessWdTimeoutMsiFifo = 0x00A001C4,\n \tHWPfQmgrDepthLog2Grp = 0x00A00200,\n \tHWPfQmgrTholdGrp = 0x00A00300,\n \tHWPfQmgrGrpTmplateReg0Indx = 0x00A00600,\n@@ -48,85 +22,23 @@ enum {\n \tHWPfQmgrGrpTmplateReg3Indx = 0x00A00780,\n \tHWPfQmgrGrpTmplateReg4Indx = 0x00A00800,\n \tHWPfQmgrVfBaseAddr = 0x00A01000,\n-\tHWPfQmgrUl4GWeightRrVf = 0x00A02000,\n-\tHWPfQmgrDl4GWeightRrVf = 0x00A02100,\n-\tHWPfQmgrUl5GWeightRrVf = 0x00A02200,\n-\tHWPfQmgrDl5GWeightRrVf = 0x00A02300,\n-\tHWPfQmgrMldWeightRrVf = 0x00A02400,\n \tHWPfQmgrArbQDepthGrp = 0x00A02F00,\n \tHWPfQmgrGrpFunction0 = 0x00A02F40,\n-\tHWPfQmgrGrpFunction1 = 0x00A02F44,\n \tHWPfQmgrGrpPriority = 0x00A02F48,\n-\tHWPfQmgrWeightSync = 0x00A03000,\n \tHWPfQmgrAqEnableVf = 0x00A10000,\n-\tHWPfQmgrAqResetVf = 0x00A20000,\n \tHWPfQmgrRingSizeVf = 0x00A20004,\n \tHWPfQmgrGrpDepthLog20Vf = 0x00A20008,\n \tHWPfQmgrGrpDepthLog21Vf = 0x00A2000C,\n-\tHWPfQmgrGrpFunction0Vf = 0x00A20010,\n-\tHWPfQmgrGrpFunction1Vf = 0x00A20014,\n \tHWPfDmaConfig0Reg = 0x00B80000,\n \tHWPfDmaConfig1Reg = 0x00B80004,\n \tHWPfDmaQmgrAddrReg = 0x00B80008,\n-\tHWPfDmaSoftResetReg = 0x00B8000C,\n \tHWPfDmaAxcacheReg = 0x00B80010,\n-\tHWPfDmaVersionReg = 0x00B80014,\n-\tHWPfDmaFrameThreshold = 0x00B80018,\n-\tHWPfDmaTimestampLo = 0x00B8001C,\n-\tHWPfDmaTimestampHi = 0x00B80020,\n-\tHWPfDmaAxiStatus = 0x00B80028,\n \tHWPfDmaAxiControl = 0x00B8002C,\n-\tHWPfDmaNoQmgr = 0x00B80030,\n-\tHWPfDmaQosScale = 0x00B80034,\n \tHWPfDmaQmanen = 0x00B80040,\n-\tHWPfDmaQmgrQosBase = 0x00B80060,\n-\tHWPfDmaFecClkGatingEnable = 0x00B80080,\n-\tHWPfDmaPmEnable = 0x00B80084,\n-\tHWPfDmaQosEnable = 0x00B80088,\n-\tHWPfDmaHarqWeightedRrFrameThreshold = 0x00B800B0,\n-\tHWPfDmaDataSmallWeightedRrFrameThresh = 0x00B800B4,\n-\tHWPfDmaDataLargeWeightedRrFrameThresh = 0x00B800B8,\n-\tHWPfDmaInboundCbMaxSize = 0x00B800BC,\n \tHWPfDmaInboundDrainDataSize = 0x00B800C0,\n \tHWPfDmaVfDdrBaseRw = 0x00B80400,\n-\tHWPfDmaCmplTmOutCnt = 0x00B80800,\n-\tHWPfDmaProcTmOutCnt = 0x00B80804,\n-\tHWPfDmaStatusRrespBresp = 0x00B80810,\n-\tHWPfDmaCfgRrespBresp = 0x00B80814,\n-\tHWPfDmaStatusMemParErr = 0x00B80818,\n-\tHWPfDmaCfgMemParErrEn = 0x00B8081C,\n-\tHWPfDmaStatusDmaHwErr = 0x00B80820,\n-\tHWPfDmaCfgDmaHwErrEn = 0x00B80824,\n-\tHWPfDmaStatusFecCoreErr = 0x00B80828,\n-\tHWPfDmaCfgFecCoreErrEn = 0x00B8082C,\n-\tHWPfDmaStatusFcwDescrErr = 0x00B80830,\n-\tHWPfDmaCfgFcwDescrErrEn = 0x00B80834,\n-\tHWPfDmaStatusBlockTransmit = 0x00B80838,\n-\tHWPfDmaBlockOnErrEn = 0x00B8083C,\n-\tHWPfDmaStatusFlushDma = 0x00B80840,\n-\tHWPfDmaFlushDmaOnErrEn = 0x00B80844,\n-\tHWPfDmaStatusSdoneFifoFull = 0x00B80848,\n-\tHWPfDmaStatusDescriptorErrLoVf = 0x00B8084C,\n-\tHWPfDmaStatusDescriptorErrHiVf = 0x00B80850,\n-\tHWPfDmaStatusFcwErrLoVf = 0x00B80854,\n-\tHWPfDmaStatusFcwErrHiVf = 0x00B80858,\n-\tHWPfDmaStatusDataErrLoVf = 0x00B8085C,\n-\tHWPfDmaStatusDataErrHiVf = 0x00B80860,\n-\tHWPfDmaCfgMsiEnSoftwareErr = 0x00B80864,\n \tHWPfDmaDescriptorSignatuture = 0x00B80868,\n-\tHWPfDmaFcwSignature = 0x00B8086C,\n \tHWPfDmaErrorDetectionEn = 0x00B80870,\n-\tHWPfDmaErrCntrlFifoDebug = 0x00B8087C,\n-\tHWPfDmaStatusToutData = 0x00B80880,\n-\tHWPfDmaStatusToutDesc = 0x00B80884,\n-\tHWPfDmaStatusToutUnexpData = 0x00B80888,\n-\tHWPfDmaStatusToutUnexpDesc = 0x00B8088C,\n-\tHWPfDmaStatusToutProcess = 0x00B80890,\n-\tHWPfDmaConfigCtoutOutDataEn = 0x00B808A0,\n-\tHWPfDmaConfigCtoutOutDescrEn = 0x00B808A4,\n-\tHWPfDmaConfigUnexpComplDataEn = 0x00B808A8,\n-\tHWPfDmaConfigUnexpComplDescrEn = 0x00B808AC,\n-\tHWPfDmaConfigPtoutOutEn = 0x00B808B0,\n \tHWPfDmaFec5GulDescBaseLoRegVf = 0x00B88020,\n \tHWPfDmaFec5GulDescBaseHiRegVf = 0x00B88024,\n \tHWPfDmaFec5GulRespPtrLoRegVf = 0x00B88028,\n@@ -143,414 +55,34 @@ enum {\n \tHWPfDmaFec4GdlDescBaseHiRegVf = 0x00B88084,\n \tHWPfDmaFec4GdlRespPtrLoRegVf = 0x00B88088,\n \tHWPfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C,\n-\tHWPfDmaVfDdrBaseRangeRo = 0x00B880A0,\n-\tHWPfQosmonACntrlReg = 0x00B90000,\n \tHWPfQosmonAEvalOverflow0 = 0x00B90008,\n-\tHWPfQosmonAEvalOverflow1 = 0x00B9000C,\n-\tHWPfQosmonADivTerm = 0x00B90010,\n-\tHWPfQosmonATickTerm = 0x00B90014,\n-\tHWPfQosmonAEvalTerm = 0x00B90018,\n-\tHWPfQosmonAAveTerm = 0x00B9001C,\n-\tHWPfQosmonAForceEccErr = 0x00B90020,\n-\tHWPfQosmonAEccErrDetect = 0x00B90024,\n-\tHWPfQosmonAIterationConfig0Low = 0x00B90060,\n-\tHWPfQosmonAIterationConfig0High = 0x00B90064,\n-\tHWPfQosmonAIterationConfig1Low = 0x00B90068,\n-\tHWPfQosmonAIterationConfig1High = 0x00B9006C,\n-\tHWPfQosmonAIterationConfig2Low = 0x00B90070,\n-\tHWPfQosmonAIterationConfig2High = 0x00B90074,\n-\tHWPfQosmonAIterationConfig3Low = 0x00B90078,\n-\tHWPfQosmonAIterationConfig3High = 0x00B9007C,\n-\tHWPfQosmonAEvalMemAddr = 0x00B90080,\n-\tHWPfQosmonAEvalMemData = 0x00B90084,\n-\tHWPfQosmonAXaction = 0x00B900C0,\n-\tHWPfQosmonARemThres1Vf = 0x00B90400,\n-\tHWPfQosmonAThres2Vf = 0x00B90404,\n-\tHWPfQosmonAWeiFracVf = 0x00B90408,\n-\tHWPfQosmonARrWeiVf = 0x00B9040C,\n \tHWPfPermonACntrlRegVf = 0x00B98000,\n-\tHWPfPermonACountVf = 0x00B98008,\n-\tHWPfPermonAKCntLoVf = 0x00B98010,\n-\tHWPfPermonAKCntHiVf = 0x00B98014,\n-\tHWPfPermonADeltaCntLoVf = 0x00B98020,\n-\tHWPfPermonADeltaCntHiVf = 0x00B98024,\n-\tHWPfPermonAVersionReg = 0x00B9C000,\n-\tHWPfPermonACbControlFec = 0x00B9C0F0,\n-\tHWPfPermonADltTimerLoFec = 0x00B9C0F4,\n-\tHWPfPermonADltTimerHiFec = 0x00B9C0F8,\n-\tHWPfPermonACbCountFec = 0x00B9C100,\n-\tHWPfPermonAAccExecTimerLoFec = 0x00B9C104,\n-\tHWPfPermonAAccExecTimerHiFec = 0x00B9C108,\n-\tHWPfPermonAExecTimerMinFec = 0x00B9C200,\n-\tHWPfPermonAExecTimerMaxFec = 0x00B9C204,\n-\tHWPfPermonAControlBusMon = 0x00B9C400,\n-\tHWPfPermonAConfigBusMon = 0x00B9C404,\n-\tHWPfPermonASkipCountBusMon = 0x00B9C408,\n-\tHWPfPermonAMinLatBusMon = 0x00B9C40C,\n-\tHWPfPermonAMaxLatBusMon = 0x00B9C500,\n-\tHWPfPermonATotalLatLowBusMon = 0x00B9C504,\n-\tHWPfPermonATotalLatUpperBusMon = 0x00B9C508,\n-\tHWPfPermonATotalReqCntBusMon = 0x00B9C50C,\n-\tHWPfQosmonBCntrlReg = 0x00BA0000,\n \tHWPfQosmonBEvalOverflow0 = 0x00BA0008,\n-\tHWPfQosmonBEvalOverflow1 = 0x00BA000C,\n-\tHWPfQosmonBDivTerm = 0x00BA0010,\n-\tHWPfQosmonBTickTerm = 0x00BA0014,\n-\tHWPfQosmonBEvalTerm = 0x00BA0018,\n-\tHWPfQosmonBAveTerm = 0x00BA001C,\n-\tHWPfQosmonBForceEccErr = 0x00BA0020,\n-\tHWPfQosmonBEccErrDetect = 0x00BA0024,\n-\tHWPfQosmonBIterationConfig0Low = 0x00BA0060,\n-\tHWPfQosmonBIterationConfig0High = 0x00BA0064,\n-\tHWPfQosmonBIterationConfig1Low = 0x00BA0068,\n-\tHWPfQosmonBIterationConfig1High = 0x00BA006C,\n-\tHWPfQosmonBIterationConfig2Low = 0x00BA0070,\n-\tHWPfQosmonBIterationConfig2High = 0x00BA0074,\n-\tHWPfQosmonBIterationConfig3Low = 0x00BA0078,\n-\tHWPfQosmonBIterationConfig3High = 0x00BA007C,\n-\tHWPfQosmonBEvalMemAddr = 0x00BA0080,\n-\tHWPfQosmonBEvalMemData = 0x00BA0084,\n-\tHWPfQosmonBXaction = 0x00BA00C0,\n-\tHWPfQosmonBRemThres1Vf = 0x00BA0400,\n-\tHWPfQosmonBThres2Vf = 0x00BA0404,\n-\tHWPfQosmonBWeiFracVf = 0x00BA0408,\n-\tHWPfQosmonBRrWeiVf = 0x00BA040C,\n \tHWPfPermonBCntrlRegVf = 0x00BA8000,\n-\tHWPfPermonBCountVf = 0x00BA8008,\n-\tHWPfPermonBKCntLoVf = 0x00BA8010,\n-\tHWPfPermonBKCntHiVf = 0x00BA8014,\n-\tHWPfPermonBDeltaCntLoVf = 0x00BA8020,\n-\tHWPfPermonBDeltaCntHiVf = 0x00BA8024,\n-\tHWPfPermonBVersionReg = 0x00BAC000,\n-\tHWPfPermonBCbControlFec = 0x00BAC0F0,\n-\tHWPfPermonBDltTimerLoFec = 0x00BAC0F4,\n-\tHWPfPermonBDltTimerHiFec = 0x00BAC0F8,\n-\tHWPfPermonBCbCountFec = 0x00BAC100,\n-\tHWPfPermonBAccExecTimerLoFec = 0x00BAC104,\n-\tHWPfPermonBAccExecTimerHiFec = 0x00BAC108,\n-\tHWPfPermonBExecTimerMinFec = 0x00BAC200,\n-\tHWPfPermonBExecTimerMaxFec = 0x00BAC204,\n-\tHWPfPermonBControlBusMon = 0x00BAC400,\n-\tHWPfPermonBConfigBusMon = 0x00BAC404,\n-\tHWPfPermonBSkipCountBusMon = 0x00BAC408,\n-\tHWPfPermonBMinLatBusMon = 0x00BAC40C,\n-\tHWPfPermonBMaxLatBusMon = 0x00BAC500,\n-\tHWPfPermonBTotalLatLowBusMon = 0x00BAC504,\n-\tHWPfPermonBTotalLatUpperBusMon = 0x00BAC508,\n-\tHWPfPermonBTotalReqCntBusMon = 0x00BAC50C,\n-\tHwPfFabI2MArbCntrlReg = 0x00BB0000,\n \tHWPfFabricMode = 0x00BB1000,\n-\tHwPfFabI2MGrp0DebugReg = 0x00BBF000,\n-\tHwPfFabI2MGrp1DebugReg = 0x00BBF004,\n-\tHwPfFabI2MGrp2DebugReg = 0x00BBF008,\n-\tHwPfFabI2MGrp3DebugReg = 0x00BBF00C,\n-\tHwPfFabI2MBuf0DebugReg = 0x00BBF010,\n-\tHwPfFabI2MBuf1DebugReg = 0x00BBF014,\n-\tHwPfFabI2MBuf2DebugReg = 0x00BBF018,\n-\tHwPfFabI2MBuf3DebugReg = 0x00BBF01C,\n-\tHwPfFabM2IBuf0Grp0DebugReg = 0x00BBF020,\n-\tHwPfFabM2IBuf1Grp0DebugReg = 0x00BBF024,\n-\tHwPfFabM2IBuf0Grp1DebugReg = 0x00BBF028,\n-\tHwPfFabM2IBuf1Grp1DebugReg = 0x00BBF02C,\n-\tHwPfFabM2IBuf0Grp2DebugReg = 0x00BBF030,\n-\tHwPfFabM2IBuf1Grp2DebugReg = 0x00BBF034,\n-\tHwPfFabM2IBuf0Grp3DebugReg = 0x00BBF038,\n-\tHwPfFabM2IBuf1Grp3DebugReg = 0x00BBF03C,\n \tHWPfFecUl5gCntrlReg = 0x00BC0000,\n-\tHWPfFecUl5gI2MThreshReg = 0x00BC0004,\n-\tHWPfFecUl5gVersionReg = 0x00BC0100,\n-\tHWPfFecUl5gFcwStatusReg = 0x00BC0104,\n-\tHWPfFecUl5gWarnReg = 0x00BC0108,\n \tHwPfFecUl5gIbDebugReg = 0x00BC0200,\n-\tHwPfFecUl5gObLlrDebugReg = 0x00BC0204,\n-\tHwPfFecUl5gObHarqDebugReg = 0x00BC0208,\n-\tHwPfFecUl5g1CntrlReg = 0x00BC1000,\n-\tHwPfFecUl5g1I2MThreshReg = 0x00BC1004,\n-\tHwPfFecUl5g1VersionReg = 0x00BC1100,\n-\tHwPfFecUl5g1FcwStatusReg = 0x00BC1104,\n-\tHwPfFecUl5g1WarnReg = 0x00BC1108,\n-\tHwPfFecUl5g1IbDebugReg = 0x00BC1200,\n-\tHwPfFecUl5g1ObLlrDebugReg = 0x00BC1204,\n-\tHwPfFecUl5g1ObHarqDebugReg = 0x00BC1208,\n-\tHwPfFecUl5g2CntrlReg = 0x00BC2000,\n-\tHwPfFecUl5g2I2MThreshReg = 0x00BC2004,\n-\tHwPfFecUl5g2VersionReg = 0x00BC2100,\n-\tHwPfFecUl5g2FcwStatusReg = 0x00BC2104,\n-\tHwPfFecUl5g2WarnReg = 0x00BC2108,\n-\tHwPfFecUl5g2IbDebugReg = 0x00BC2200,\n-\tHwPfFecUl5g2ObLlrDebugReg = 0x00BC2204,\n-\tHwPfFecUl5g2ObHarqDebugReg = 0x00BC2208,\n-\tHwPfFecUl5g3CntrlReg = 0x00BC3000,\n-\tHwPfFecUl5g3I2MThreshReg = 0x00BC3004,\n-\tHwPfFecUl5g3VersionReg = 0x00BC3100,\n-\tHwPfFecUl5g3FcwStatusReg = 0x00BC3104,\n-\tHwPfFecUl5g3WarnReg = 0x00BC3108,\n-\tHwPfFecUl5g3IbDebugReg = 0x00BC3200,\n-\tHwPfFecUl5g3ObLlrDebugReg = 0x00BC3204,\n-\tHwPfFecUl5g3ObHarqDebugReg = 0x00BC3208,\n-\tHwPfFecUl5g4CntrlReg = 0x00BC4000,\n-\tHwPfFecUl5g4I2MThreshReg = 0x00BC4004,\n-\tHwPfFecUl5g4VersionReg = 0x00BC4100,\n-\tHwPfFecUl5g4FcwStatusReg = 0x00BC4104,\n-\tHwPfFecUl5g4WarnReg = 0x00BC4108,\n-\tHwPfFecUl5g4IbDebugReg = 0x00BC4200,\n-\tHwPfFecUl5g4ObLlrDebugReg = 0x00BC4204,\n-\tHwPfFecUl5g4ObHarqDebugReg = 0x00BC4208,\n-\tHwPfFecUl5g5CntrlReg = 0x00BC5000,\n-\tHwPfFecUl5g5I2MThreshReg = 0x00BC5004,\n-\tHwPfFecUl5g5VersionReg = 0x00BC5100,\n-\tHwPfFecUl5g5FcwStatusReg = 0x00BC5104,\n-\tHwPfFecUl5g5WarnReg = 0x00BC5108,\n-\tHwPfFecUl5g5IbDebugReg = 0x00BC5200,\n-\tHwPfFecUl5g5ObLlrDebugReg = 0x00BC5204,\n-\tHwPfFecUl5g5ObHarqDebugReg = 0x00BC5208,\n-\tHwPfFecUl5g6CntrlReg = 0x00BC6000,\n-\tHwPfFecUl5g6I2MThreshReg = 0x00BC6004,\n-\tHwPfFecUl5g6VersionReg = 0x00BC6100,\n-\tHwPfFecUl5g6FcwStatusReg = 0x00BC6104,\n-\tHwPfFecUl5g6WarnReg = 0x00BC6108,\n-\tHwPfFecUl5g6IbDebugReg = 0x00BC6200,\n-\tHwPfFecUl5g6ObLlrDebugReg = 0x00BC6204,\n-\tHwPfFecUl5g6ObHarqDebugReg = 0x00BC6208,\n-\tHwPfFecUl5g7CntrlReg = 0x00BC7000,\n-\tHwPfFecUl5g7I2MThreshReg = 0x00BC7004,\n-\tHwPfFecUl5g7VersionReg = 0x00BC7100,\n-\tHwPfFecUl5g7FcwStatusReg = 0x00BC7104,\n-\tHwPfFecUl5g7WarnReg = 0x00BC7108,\n-\tHwPfFecUl5g7IbDebugReg = 0x00BC7200,\n-\tHwPfFecUl5g7ObLlrDebugReg = 0x00BC7204,\n-\tHwPfFecUl5g7ObHarqDebugReg = 0x00BC7208,\n-\tHwPfFecUl5g8CntrlReg = 0x00BC8000,\n-\tHwPfFecUl5g8I2MThreshReg = 0x00BC8004,\n-\tHwPfFecUl5g8VersionReg = 0x00BC8100,\n-\tHwPfFecUl5g8FcwStatusReg = 0x00BC8104,\n-\tHwPfFecUl5g8WarnReg = 0x00BC8108,\n-\tHwPfFecUl5g8IbDebugReg = 0x00BC8200,\n-\tHwPfFecUl5g8ObLlrDebugReg = 0x00BC8204,\n-\tHwPfFecUl5g8ObHarqDebugReg = 0x00BC8208,\n-\tHWPfFecDl5gCntrlReg = 0x00BCF000,\n-\tHWPfFecDl5gI2MThreshReg = 0x00BCF004,\n-\tHWPfFecDl5gVersionReg = 0x00BCF100,\n-\tHWPfFecDl5gFcwStatusReg = 0x00BCF104,\n-\tHWPfFecDl5gWarnReg = 0x00BCF108,\n-\tHWPfFecUlVersionReg = 0x00BD0000,\n-\tHWPfFecUlControlReg = 0x00BD0004,\n-\tHWPfFecUlStatusReg = 0x00BD0008,\n-\tHWPfFecDlVersionReg = 0x00BDF000,\n-\tHWPfFecDlClusterConfigReg = 0x00BDF004,\n-\tHWPfFecDlBurstThres = 0x00BDF00C,\n-\tHWPfFecDlClusterStatusReg0 = 0x00BDF040,\n-\tHWPfFecDlClusterStatusReg1 = 0x00BDF044,\n-\tHWPfFecDlClusterStatusReg2 = 0x00BDF048,\n-\tHWPfFecDlClusterStatusReg3 = 0x00BDF04C,\n-\tHWPfFecDlClusterStatusReg4 = 0x00BDF050,\n-\tHWPfFecDlClusterStatusReg5 = 0x00BDF054,\n-\tHWPfChaFabPllPllrst = 0x00C40000,\n-\tHWPfChaFabPllClk0 = 0x00C40004,\n-\tHWPfChaFabPllClk1 = 0x00C40008,\n-\tHWPfChaFabPllBwadj = 0x00C4000C,\n-\tHWPfChaFabPllLbw = 0x00C40010,\n-\tHWPfChaFabPllResetq = 0x00C40014,\n-\tHWPfChaFabPllPhshft0 = 0x00C40018,\n-\tHWPfChaFabPllPhshft1 = 0x00C4001C,\n-\tHWPfChaFabPllDivq0 = 0x00C40020,\n-\tHWPfChaFabPllDivq1 = 0x00C40024,\n-\tHWPfChaFabPllDivq2 = 0x00C40028,\n-\tHWPfChaFabPllDivq3 = 0x00C4002C,\n-\tHWPfChaFabPllDivq4 = 0x00C40030,\n-\tHWPfChaFabPllDivq5 = 0x00C40034,\n-\tHWPfChaFabPllDivq6 = 0x00C40038,\n-\tHWPfChaFabPllDivq7 = 0x00C4003C,\n-\tHWPfChaDl5gPllPllrst = 0x00C40080,\n-\tHWPfChaDl5gPllClk0 = 0x00C40084,\n-\tHWPfChaDl5gPllClk1 = 0x00C40088,\n-\tHWPfChaDl5gPllBwadj = 0x00C4008C,\n-\tHWPfChaDl5gPllLbw = 0x00C40090,\n-\tHWPfChaDl5gPllResetq = 0x00C40094,\n \tHWPfChaDl5gPllPhshft0 = 0x00C40098,\n-\tHWPfChaDl5gPllPhshft1 = 0x00C4009C,\n-\tHWPfChaDl5gPllDivq0 = 0x00C400A0,\n-\tHWPfChaDl5gPllDivq1 = 0x00C400A4,\n-\tHWPfChaDl5gPllDivq2 = 0x00C400A8,\n-\tHWPfChaDl5gPllDivq3 = 0x00C400AC,\n-\tHWPfChaDl5gPllDivq4 = 0x00C400B0,\n-\tHWPfChaDl5gPllDivq5 = 0x00C400B4,\n-\tHWPfChaDl5gPllDivq6 = 0x00C400B8,\n-\tHWPfChaDl5gPllDivq7 = 0x00C400BC,\n-\tHWPfChaDl4gPllPllrst = 0x00C40100,\n-\tHWPfChaDl4gPllClk0 = 0x00C40104,\n-\tHWPfChaDl4gPllClk1 = 0x00C40108,\n-\tHWPfChaDl4gPllBwadj = 0x00C4010C,\n-\tHWPfChaDl4gPllLbw = 0x00C40110,\n-\tHWPfChaDl4gPllResetq = 0x00C40114,\n-\tHWPfChaDl4gPllPhshft0 = 0x00C40118,\n-\tHWPfChaDl4gPllPhshft1 = 0x00C4011C,\n-\tHWPfChaDl4gPllDivq0 = 0x00C40120,\n-\tHWPfChaDl4gPllDivq1 = 0x00C40124,\n-\tHWPfChaDl4gPllDivq2 = 0x00C40128,\n-\tHWPfChaDl4gPllDivq3 = 0x00C4012C,\n-\tHWPfChaDl4gPllDivq4 = 0x00C40130,\n-\tHWPfChaDl4gPllDivq5 = 0x00C40134,\n-\tHWPfChaDl4gPllDivq6 = 0x00C40138,\n-\tHWPfChaDl4gPllDivq7 = 0x00C4013C,\n-\tHWPfChaUl5gPllPllrst = 0x00C40180,\n-\tHWPfChaUl5gPllClk0 = 0x00C40184,\n-\tHWPfChaUl5gPllClk1 = 0x00C40188,\n-\tHWPfChaUl5gPllBwadj = 0x00C4018C,\n-\tHWPfChaUl5gPllLbw = 0x00C40190,\n-\tHWPfChaUl5gPllResetq = 0x00C40194,\n-\tHWPfChaUl5gPllPhshft0 = 0x00C40198,\n-\tHWPfChaUl5gPllPhshft1 = 0x00C4019C,\n-\tHWPfChaUl5gPllDivq0 = 0x00C401A0,\n-\tHWPfChaUl5gPllDivq1 = 0x00C401A4,\n-\tHWPfChaUl5gPllDivq2 = 0x00C401A8,\n-\tHWPfChaUl5gPllDivq3 = 0x00C401AC,\n-\tHWPfChaUl5gPllDivq4 = 0x00C401B0,\n-\tHWPfChaUl5gPllDivq5 = 0x00C401B4,\n-\tHWPfChaUl5gPllDivq6 = 0x00C401B8,\n-\tHWPfChaUl5gPllDivq7 = 0x00C401BC,\n-\tHWPfChaUl4gPllPllrst = 0x00C40200,\n-\tHWPfChaUl4gPllClk0 = 0x00C40204,\n-\tHWPfChaUl4gPllClk1 = 0x00C40208,\n-\tHWPfChaUl4gPllBwadj = 0x00C4020C,\n-\tHWPfChaUl4gPllLbw = 0x00C40210,\n-\tHWPfChaUl4gPllResetq = 0x00C40214,\n-\tHWPfChaUl4gPllPhshft0 = 0x00C40218,\n-\tHWPfChaUl4gPllPhshft1 = 0x00C4021C,\n-\tHWPfChaUl4gPllDivq0 = 0x00C40220,\n-\tHWPfChaUl4gPllDivq1 = 0x00C40224,\n-\tHWPfChaUl4gPllDivq2 = 0x00C40228,\n-\tHWPfChaUl4gPllDivq3 = 0x00C4022C,\n-\tHWPfChaUl4gPllDivq4 = 0x00C40230,\n-\tHWPfChaUl4gPllDivq5 = 0x00C40234,\n-\tHWPfChaUl4gPllDivq6 = 0x00C40238,\n-\tHWPfChaUl4gPllDivq7 = 0x00C4023C,\n-\tHWPfChaDdrPllPllrst = 0x00C40280,\n-\tHWPfChaDdrPllClk0 = 0x00C40284,\n-\tHWPfChaDdrPllClk1 = 0x00C40288,\n-\tHWPfChaDdrPllBwadj = 0x00C4028C,\n-\tHWPfChaDdrPllLbw = 0x00C40290,\n-\tHWPfChaDdrPllResetq = 0x00C40294,\n-\tHWPfChaDdrPllPhshft0 = 0x00C40298,\n-\tHWPfChaDdrPllPhshft1 = 0x00C4029C,\n-\tHWPfChaDdrPllDivq0 = 0x00C402A0,\n-\tHWPfChaDdrPllDivq1 = 0x00C402A4,\n-\tHWPfChaDdrPllDivq2 = 0x00C402A8,\n-\tHWPfChaDdrPllDivq3 = 0x00C402AC,\n-\tHWPfChaDdrPllDivq4 = 0x00C402B0,\n-\tHWPfChaDdrPllDivq5 = 0x00C402B4,\n-\tHWPfChaDdrPllDivq6 = 0x00C402B8,\n-\tHWPfChaDdrPllDivq7 = 0x00C402BC,\n-\tHWPfChaErrStatus = 0x00C40400,\n-\tHWPfChaErrMask = 0x00C40404,\n-\tHWPfChaDebugPcieMsiFifo = 0x00C40410,\n-\tHWPfChaDebugDdrMsiFifo = 0x00C40414,\n-\tHWPfChaDebugMiscMsiFifo = 0x00C40418,\n-\tHWPfChaPwmSet = 0x00C40420,\n-\tHWPfChaDdrRstStatus = 0x00C40430,\n \tHWPfChaDdrStDoneStatus = 0x00C40434,\n \tHWPfChaDdrWbRstCfg = 0x00C40438,\n \tHWPfChaDdrApbRstCfg = 0x00C4043C,\n \tHWPfChaDdrPhyRstCfg = 0x00C40440,\n \tHWPfChaDdrCpuRstCfg = 0x00C40444,\n \tHWPfChaDdrSifRstCfg = 0x00C40448,\n-\tHWPfChaPadcfgPcomp0 = 0x00C41000,\n-\tHWPfChaPadcfgNcomp0 = 0x00C41004,\n-\tHWPfChaPadcfgOdt0 = 0x00C41008,\n-\tHWPfChaPadcfgProtect0 = 0x00C4100C,\n-\tHWPfChaPreemphasisProtect0 = 0x00C41010,\n-\tHWPfChaPreemphasisCompen0 = 0x00C41040,\n-\tHWPfChaPreemphasisOdten0 = 0x00C41044,\n-\tHWPfChaPadcfgPcomp1 = 0x00C41100,\n-\tHWPfChaPadcfgNcomp1 = 0x00C41104,\n-\tHWPfChaPadcfgOdt1 = 0x00C41108,\n-\tHWPfChaPadcfgProtect1 = 0x00C4110C,\n-\tHWPfChaPreemphasisProtect1 = 0x00C41110,\n-\tHWPfChaPreemphasisCompen1 = 0x00C41140,\n-\tHWPfChaPreemphasisOdten1 = 0x00C41144,\n-\tHWPfChaPadcfgPcomp2 = 0x00C41200,\n-\tHWPfChaPadcfgNcomp2 = 0x00C41204,\n-\tHWPfChaPadcfgOdt2 = 0x00C41208,\n-\tHWPfChaPadcfgProtect2 = 0x00C4120C,\n-\tHWPfChaPreemphasisProtect2 = 0x00C41210,\n-\tHWPfChaPreemphasisCompen2 = 0x00C41240,\n-\tHWPfChaPreemphasisOdten4 = 0x00C41444,\n-\tHWPfChaPreemphasisOdten2 = 0x00C41244,\n-\tHWPfChaPadcfgPcomp3 = 0x00C41300,\n-\tHWPfChaPadcfgNcomp3 = 0x00C41304,\n-\tHWPfChaPadcfgOdt3 = 0x00C41308,\n-\tHWPfChaPadcfgProtect3 = 0x00C4130C,\n-\tHWPfChaPreemphasisProtect3 = 0x00C41310,\n-\tHWPfChaPreemphasisCompen3 = 0x00C41340,\n-\tHWPfChaPreemphasisOdten3 = 0x00C41344,\n-\tHWPfChaPadcfgPcomp4 = 0x00C41400,\n-\tHWPfChaPadcfgNcomp4 = 0x00C41404,\n-\tHWPfChaPadcfgOdt4 = 0x00C41408,\n-\tHWPfChaPadcfgProtect4 = 0x00C4140C,\n-\tHWPfChaPreemphasisProtect4 = 0x00C41410,\n-\tHWPfChaPreemphasisCompen4 = 0x00C41440,\n-\tHWPfHiVfToPfDbellVf = 0x00C80000,\n-\tHWPfHiPfToVfDbellVf = 0x00C80008,\n-\tHWPfHiInfoRingBaseLoVf = 0x00C80010,\n-\tHWPfHiInfoRingBaseHiVf = 0x00C80014,\n-\tHWPfHiInfoRingPointerVf = 0x00C80018,\n-\tHWPfHiInfoRingIntWrEnVf = 0x00C80020,\n-\tHWPfHiInfoRingPf2VfWrEnVf = 0x00C80024,\n-\tHWPfHiMsixVectorMapperVf = 0x00C80060,\n-\tHWPfHiModuleVersionReg = 0x00C84000,\n-\tHWPfHiIosf2axiErrLogReg = 0x00C84004,\n-\tHWPfHiHardResetReg = 0x00C84008,\n \tHWPfHi5GHardResetReg = 0x00C8400C,\n \tHWPfHiInfoRingBaseLoRegPf = 0x00C84010,\n \tHWPfHiInfoRingBaseHiRegPf = 0x00C84014,\n \tHWPfHiInfoRingPointerRegPf = 0x00C84018,\n \tHWPfHiInfoRingIntWrEnRegPf = 0x00C84020,\n \tHWPfHiInfoRingVf2pfLoWrEnReg = 0x00C84024,\n-\tHWPfHiInfoRingVf2pfHiWrEnReg = 0x00C84028,\n-\tHWPfHiLogParityErrStatusReg = 0x00C8402C,\n-\tHWPfHiLogDataParityErrorVfStatusLo = 0x00C84030,\n-\tHWPfHiLogDataParityErrorVfStatusHi = 0x00C84034,\n \tHWPfHiBlockTransmitOnErrorEn = 0x00C84038,\n \tHWPfHiCfgMsiIntWrEnRegPf = 0x00C84040,\n \tHWPfHiCfgMsiVf2pfLoWrEnReg = 0x00C84044,\n-\tHWPfHiCfgMsiVf2pfHighWrEnReg = 0x00C84048,\n-\tHWPfHiMsixVectorMapperPf = 0x00C84060,\n-\tHWPfHiApbWrWaitTime = 0x00C84100,\n-\tHWPfHiXCounterMaxValue = 0x00C84104,\n \tHWPfHiPfMode = 0x00C84108,\n \tHWPfHiClkGateHystReg = 0x00C8410C,\n-\tHWPfHiSnoopBitsReg = 0x00C84110,\n \tHWPfHiMsiDropEnableReg = 0x00C84114,\n-\tHWPfHiMsiStatReg = 0x00C84120,\n-\tHWPfHiFifoOflStatReg = 0x00C84124,\n-\tHWPfHiHiDebugReg = 0x00C841F4,\n-\tHWPfHiDebugMemSnoopMsiFifo = 0x00C841F8,\n-\tHWPfHiDebugMemSnoopInputFifo = 0x00C841FC,\n-\tHWPfHiMsixMappingConfig = 0x00C84200,\n-\tHWPfHiJunkReg = 0x00C8FF00,\n-\tHWPfDdrUmmcVer = 0x00D00000,\n-\tHWPfDdrUmmcCap = 0x00D00010,\n \tHWPfDdrUmmcCtrl = 0x00D00020,\n-\tHWPfDdrMpcPe = 0x00D00080,\n-\tHWPfDdrMpcPpri3 = 0x00D00090,\n-\tHWPfDdrMpcPpri2 = 0x00D000A0,\n-\tHWPfDdrMpcPpri1 = 0x00D000B0,\n-\tHWPfDdrMpcPpri0 = 0x00D000C0,\n-\tHWPfDdrMpcPrwgrpCtrl = 0x00D000D0,\n-\tHWPfDdrMpcPbw7 = 0x00D000E0,\n-\tHWPfDdrMpcPbw6 = 0x00D000F0,\n-\tHWPfDdrMpcPbw5 = 0x00D00100,\n-\tHWPfDdrMpcPbw4 = 0x00D00110,\n-\tHWPfDdrMpcPbw3 = 0x00D00120,\n-\tHWPfDdrMpcPbw2 = 0x00D00130,\n-\tHWPfDdrMpcPbw1 = 0x00D00140,\n-\tHWPfDdrMpcPbw0 = 0x00D00150,\n-\tHWPfDdrMemoryInit = 0x00D00200,\n-\tHWPfDdrMemoryInitDone = 0x00D00210,\n \tHWPfDdrMemInitPhyTrng0 = 0x00D00240,\n-\tHWPfDdrMemInitPhyTrng1 = 0x00D00250,\n-\tHWPfDdrMemInitPhyTrng2 = 0x00D00260,\n-\tHWPfDdrMemInitPhyTrng3 = 0x00D00270,\n \tHWPfDdrBcDram = 0x00D003C0,\n \tHWPfDdrBcAddrMap = 0x00D003D0,\n \tHWPfDdrBcRef = 0x00D003E0,\n@@ -565,502 +97,31 @@ enum {\n \tHWPfDdrBcTim8 = 0x00D00480,\n \tHWPfDdrBcTim9 = 0x00D00490,\n \tHWPfDdrBcTim10 = 0x00D004A0,\n-\tHWPfDdrBcTim12 = 0x00D004C0,\n \tHWPfDdrDfiInit = 0x00D004D0,\n-\tHWPfDdrDfiInitComplete = 0x00D004E0,\n \tHWPfDdrDfiTim0 = 0x00D004F0,\n \tHWPfDdrDfiTim1 = 0x00D00500,\n \tHWPfDdrDfiPhyUpdEn = 0x00D00530,\n-\tHWPfDdrMemStatus = 0x00D00540,\n-\tHWPfDdrUmmcErrStatus = 0x00D00550,\n-\tHWPfDdrUmmcIntStatus = 0x00D00560,\n \tHWPfDdrUmmcIntEn = 0x00D00570,\n \tHWPfDdrPhyRdLatency = 0x00D48400,\n \tHWPfDdrPhyRdLatencyDbi = 0x00D48410,\n \tHWPfDdrPhyWrLatency = 0x00D48420,\n \tHWPfDdrPhyTrngType = 0x00D48430,\n-\tHWPfDdrPhyMrsTiming2 = 0x00D48440,\n-\tHWPfDdrPhyMrsTiming0 = 0x00D48450,\n-\tHWPfDdrPhyMrsTiming1 = 0x00D48460,\n-\tHWPfDdrPhyDramTmrd = 0x00D48470,\n-\tHWPfDdrPhyDramTmod = 0x00D48480,\n-\tHWPfDdrPhyDramTwpre = 0x00D48490,\n-\tHWPfDdrPhyDramTrfc = 0x00D484A0,\n-\tHWPfDdrPhyDramTrwtp = 0x00D484B0,\n \tHWPfDdrPhyMr01Dimm = 0x00D484C0,\n \tHWPfDdrPhyMr01DimmDbi = 0x00D484D0,\n \tHWPfDdrPhyMr23Dimm = 0x00D484E0,\n \tHWPfDdrPhyMr45Dimm = 0x00D484F0,\n \tHWPfDdrPhyMr67Dimm = 0x00D48500,\n \tHWPfDdrPhyWrlvlWwRdlvlRr = 0x00D48510,\n-\tHWPfDdrPhyOdtEn = 0x00D48520,\n-\tHWPfDdrPhyFastTrng = 0x00D48530,\n-\tHWPfDdrPhyDynTrngGap = 0x00D48540,\n-\tHWPfDdrPhyDynRcalGap = 0x00D48550,\n \tHWPfDdrPhyIdletimeout = 0x00D48560,\n-\tHWPfDdrPhyRstCkeGap = 0x00D48570,\n-\tHWPfDdrPhyCkeMrsGap = 0x00D48580,\n-\tHWPfDdrPhyMemVrefMidVal = 0x00D48590,\n-\tHWPfDdrPhyVrefStep = 0x00D485A0,\n-\tHWPfDdrPhyVrefThreshold = 0x00D485B0,\n-\tHWPfDdrPhyPhyVrefMidVal = 0x00D485C0,\n \tHWPfDdrPhyDqsCountMax = 0x00D485D0,\n \tHWPfDdrPhyDqsCountNum = 0x00D485E0,\n-\tHWPfDdrPhyDramRow = 0x00D485F0,\n-\tHWPfDdrPhyDramCol = 0x00D48600,\n-\tHWPfDdrPhyDramBgBa = 0x00D48610,\n-\tHWPfDdrPhyDynamicUpdreqrel = 0x00D48620,\n-\tHWPfDdrPhyVrefLimits = 0x00D48630,\n-\tHWPfDdrPhyIdtmTcStatus = 0x00D6C020,\n \tHWPfDdrPhyIdtmFwVersion = 0x00D6C410,\n-\tHWPfDdrPhyRdlvlGateInitDelay = 0x00D70000,\n-\tHWPfDdrPhyRdenSmplabc = 0x00D70008,\n-\tHWPfDdrPhyVrefNibble0 = 0x00D7000C,\n-\tHWPfDdrPhyVrefNibble1 = 0x00D70010,\n-\tHWPfDdrPhyRdlvlGateDqsSmpl0 = 0x00D70014,\n-\tHWPfDdrPhyRdlvlGateDqsSmpl1 = 0x00D70018,\n-\tHWPfDdrPhyRdlvlGateDqsSmpl2 = 0x00D7001C,\n \tHWPfDdrPhyDqsCount = 0x00D70020,\n-\tHWPfDdrPhyWrlvlRdlvlGateStatus = 0x00D70024,\n-\tHWPfDdrPhyErrorFlags = 0x00D70028,\n-\tHWPfDdrPhyPowerDown = 0x00D70030,\n-\tHWPfDdrPhyPrbsSeedByte0 = 0x00D70034,\n-\tHWPfDdrPhyPrbsSeedByte1 = 0x00D70038,\n-\tHWPfDdrPhyPcompDq = 0x00D70040,\n-\tHWPfDdrPhyNcompDq = 0x00D70044,\n-\tHWPfDdrPhyPcompDqs = 0x00D70048,\n-\tHWPfDdrPhyNcompDqs = 0x00D7004C,\n-\tHWPfDdrPhyPcompCmd = 0x00D70050,\n-\tHWPfDdrPhyNcompCmd = 0x00D70054,\n-\tHWPfDdrPhyPcompCk = 0x00D70058,\n-\tHWPfDdrPhyNcompCk = 0x00D7005C,\n-\tHWPfDdrPhyRcalOdtDq = 0x00D70060,\n-\tHWPfDdrPhyRcalOdtDqs = 0x00D70064,\n-\tHWPfDdrPhyRcalMask1 = 0x00D70068,\n-\tHWPfDdrPhyRcalMask2 = 0x00D7006C,\n-\tHWPfDdrPhyRcalCtrl = 0x00D70070,\n-\tHWPfDdrPhyRcalCnt = 0x00D70074,\n-\tHWPfDdrPhyRcalOverride = 0x00D70078,\n-\tHWPfDdrPhyRcalGateen = 0x00D7007C,\n-\tHWPfDdrPhyCtrl = 0x00D70080,\n-\tHWPfDdrPhyWrlvlAlg = 0x00D70084,\n-\tHWPfDdrPhyRcalVreftTxcmdOdt = 0x00D70088,\n-\tHWPfDdrPhyRdlvlGateParam = 0x00D7008C,\n-\tHWPfDdrPhyRdlvlGateParam2 = 0x00D70090,\n-\tHWPfDdrPhyRcalVreftTxdata = 0x00D70094,\n-\tHWPfDdrPhyCmdIntDelay = 0x00D700A4,\n-\tHWPfDdrPhyAlertN = 0x00D700A8,\n-\tHWPfDdrPhyTrngReqWpre2tck = 0x00D700AC,\n-\tHWPfDdrPhyCmdPhaseSel = 0x00D700B4,\n-\tHWPfDdrPhyCmdDcdl = 0x00D700B8,\n-\tHWPfDdrPhyCkDcdl = 0x00D700BC,\n-\tHWPfDdrPhySwTrngCtrl1 = 0x00D700C0,\n-\tHWPfDdrPhySwTrngCtrl2 = 0x00D700C4,\n-\tHWPfDdrPhyRcalPcompRden = 0x00D700C8,\n-\tHWPfDdrPhyRcalNcompRden = 0x00D700CC,\n-\tHWPfDdrPhyRcalCompen = 0x00D700D0,\n-\tHWPfDdrPhySwTrngRdqs = 0x00D700D4,\n-\tHWPfDdrPhySwTrngWdqs = 0x00D700D8,\n-\tHWPfDdrPhySwTrngRdena = 0x00D700DC,\n-\tHWPfDdrPhySwTrngRdenb = 0x00D700E0,\n-\tHWPfDdrPhySwTrngRdenc = 0x00D700E4,\n-\tHWPfDdrPhySwTrngWdq = 0x00D700E8,\n-\tHWPfDdrPhySwTrngRdq = 0x00D700EC,\n-\tHWPfDdrPhyPcfgHmValue = 0x00D700F0,\n-\tHWPfDdrPhyPcfgTimerValue = 0x00D700F4,\n-\tHWPfDdrPhyPcfgSoftwareTraining = 0x00D700F8,\n-\tHWPfDdrPhyPcfgMcStatus = 0x00D700FC,\n-\tHWPfDdrPhyWrlvlPhRank0 = 0x00D70100,\n-\tHWPfDdrPhyRdenPhRank0 = 0x00D70104,\n-\tHWPfDdrPhyRdenIntRank0 = 0x00D70108,\n-\tHWPfDdrPhyRdqsDcdlRank0 = 0x00D7010C,\n-\tHWPfDdrPhyRdqsShadowDcdlRank0 = 0x00D70110,\n-\tHWPfDdrPhyWdqsDcdlRank0 = 0x00D70114,\n-\tHWPfDdrPhyWdmDcdlShadowRank0 = 0x00D70118,\n-\tHWPfDdrPhyWdmDcdlRank0 = 0x00D7011C,\n-\tHWPfDdrPhyDbiDcdlRank0 = 0x00D70120,\n-\tHWPfDdrPhyRdenDcdlaRank0 = 0x00D70124,\n-\tHWPfDdrPhyDbiDcdlShadowRank0 = 0x00D70128,\n-\tHWPfDdrPhyRdenDcdlbRank0 = 0x00D7012C,\n-\tHWPfDdrPhyWdqsShadowDcdlRank0 = 0x00D70130,\n-\tHWPfDdrPhyRdenDcdlcRank0 = 0x00D70134,\n-\tHWPfDdrPhyRdenShadowDcdlaRank0 = 0x00D70138,\n-\tHWPfDdrPhyWrlvlIntRank0 = 0x00D7013C,\n-\tHWPfDdrPhyRdqDcdlBit0Rank0 = 0x00D70200,\n-\tHWPfDdrPhyRdqDcdlShadowBit0Rank0 = 0x00D70204,\n-\tHWPfDdrPhyWdqDcdlBit0Rank0 = 0x00D70208,\n-\tHWPfDdrPhyWdqDcdlShadowBit0Rank0 = 0x00D7020C,\n-\tHWPfDdrPhyRdqDcdlBit1Rank0 = 0x00D70240,\n-\tHWPfDdrPhyRdqDcdlShadowBit1Rank0 = 0x00D70244,\n-\tHWPfDdrPhyWdqDcdlBit1Rank0 = 0x00D70248,\n-\tHWPfDdrPhyWdqDcdlShadowBit1Rank0 = 0x00D7024C,\n-\tHWPfDdrPhyRdqDcdlBit2Rank0 = 0x00D70280,\n-\tHWPfDdrPhyRdqDcdlShadowBit2Rank0 = 0x00D70284,\n-\tHWPfDdrPhyWdqDcdlBit2Rank0 = 0x00D70288,\n-\tHWPfDdrPhyWdqDcdlShadowBit2Rank0 = 0x00D7028C,\n-\tHWPfDdrPhyRdqDcdlBit3Rank0 = 0x00D702C0,\n-\tHWPfDdrPhyRdqDcdlShadowBit3Rank0 = 0x00D702C4,\n-\tHWPfDdrPhyWdqDcdlBit3Rank0 = 0x00D702C8,\n-\tHWPfDdrPhyWdqDcdlShadowBit3Rank0 = 0x00D702CC,\n-\tHWPfDdrPhyRdqDcdlBit4Rank0 = 0x00D70300,\n-\tHWPfDdrPhyRdqDcdlShadowBit4Rank0 = 0x00D70304,\n-\tHWPfDdrPhyWdqDcdlBit4Rank0 = 0x00D70308,\n-\tHWPfDdrPhyWdqDcdlShadowBit4Rank0 = 0x00D7030C,\n-\tHWPfDdrPhyRdqDcdlBit5Rank0 = 0x00D70340,\n-\tHWPfDdrPhyRdqDcdlShadowBit5Rank0 = 0x00D70344,\n-\tHWPfDdrPhyWdqDcdlBit5Rank0 = 0x00D70348,\n-\tHWPfDdrPhyWdqDcdlShadowBit5Rank0 = 0x00D7034C,\n-\tHWPfDdrPhyRdqDcdlBit6Rank0 = 0x00D70380,\n-\tHWPfDdrPhyRdqDcdlShadowBit6Rank0 = 0x00D70384,\n-\tHWPfDdrPhyWdqDcdlBit6Rank0 = 0x00D70388,\n-\tHWPfDdrPhyWdqDcdlShadowBit6Rank0 = 0x00D7038C,\n-\tHWPfDdrPhyRdqDcdlBit7Rank0 = 0x00D703C0,\n-\tHWPfDdrPhyRdqDcdlShadowBit7Rank0 = 0x00D703C4,\n-\tHWPfDdrPhyWdqDcdlBit7Rank0 = 0x00D703C8,\n-\tHWPfDdrPhyWdqDcdlShadowBit7Rank0 = 0x00D703CC,\n-\tHWPfDdrPhyIdtmStatus = 0x00D740D0,\n-\tHWPfDdrPhyIdtmError = 0x00D74110,\n-\tHWPfDdrPhyIdtmDebug = 0x00D74120,\n-\tHWPfDdrPhyIdtmDebugInt = 0x00D74130,\n-\tHwPfPcieLnAsicCfgovr = 0x00D80000,\n-\tHwPfPcieLnAclkmixer = 0x00D80004,\n-\tHwPfPcieLnTxrampfreq = 0x00D80008,\n-\tHwPfPcieLnLanetest = 0x00D8000C,\n-\tHwPfPcieLnDcctrl = 0x00D80010,\n-\tHwPfPcieLnDccmeas = 0x00D80014,\n-\tHwPfPcieLnDccovrAclk = 0x00D80018,\n-\tHwPfPcieLnDccovrTxa = 0x00D8001C,\n-\tHwPfPcieLnDccovrTxk = 0x00D80020,\n-\tHwPfPcieLnDccovrDclk = 0x00D80024,\n-\tHwPfPcieLnDccovrEclk = 0x00D80028,\n-\tHwPfPcieLnDcctrimAclk = 0x00D8002C,\n-\tHwPfPcieLnDcctrimTx = 0x00D80030,\n-\tHwPfPcieLnDcctrimDclk = 0x00D80034,\n-\tHwPfPcieLnDcctrimEclk = 0x00D80038,\n-\tHwPfPcieLnQuadCtrl = 0x00D8003C,\n-\tHwPfPcieLnQuadCorrIndex = 0x00D80040,\n-\tHwPfPcieLnQuadCorrStatus = 0x00D80044,\n-\tHwPfPcieLnAsicRxovr1 = 0x00D80048,\n-\tHwPfPcieLnAsicRxovr2 = 0x00D8004C,\n-\tHwPfPcieLnAsicEqinfovr = 0x00D80050,\n-\tHwPfPcieLnRxcsr = 0x00D80054,\n-\tHwPfPcieLnRxfectrl = 0x00D80058,\n-\tHwPfPcieLnRxtest = 0x00D8005C,\n-\tHwPfPcieLnEscount = 0x00D80060,\n-\tHwPfPcieLnCdrctrl = 0x00D80064,\n-\tHwPfPcieLnCdrctrl2 = 0x00D80068,\n-\tHwPfPcieLnCdrcfg0Ctrl0 = 0x00D8006C,\n-\tHwPfPcieLnCdrcfg0Ctrl1 = 0x00D80070,\n-\tHwPfPcieLnCdrcfg0Ctrl2 = 0x00D80074,\n-\tHwPfPcieLnCdrcfg1Ctrl0 = 0x00D80078,\n-\tHwPfPcieLnCdrcfg1Ctrl1 = 0x00D8007C,\n-\tHwPfPcieLnCdrcfg1Ctrl2 = 0x00D80080,\n-\tHwPfPcieLnCdrcfg2Ctrl0 = 0x00D80084,\n-\tHwPfPcieLnCdrcfg2Ctrl1 = 0x00D80088,\n-\tHwPfPcieLnCdrcfg2Ctrl2 = 0x00D8008C,\n-\tHwPfPcieLnCdrcfg3Ctrl0 = 0x00D80090,\n-\tHwPfPcieLnCdrcfg3Ctrl1 = 0x00D80094,\n-\tHwPfPcieLnCdrcfg3Ctrl2 = 0x00D80098,\n-\tHwPfPcieLnCdrphase = 0x00D8009C,\n-\tHwPfPcieLnCdrfreq = 0x00D800A0,\n-\tHwPfPcieLnCdrstatusPhase = 0x00D800A4,\n-\tHwPfPcieLnCdrstatusFreq = 0x00D800A8,\n-\tHwPfPcieLnCdroffset = 0x00D800AC,\n-\tHwPfPcieLnRxvosctl = 0x00D800B0,\n-\tHwPfPcieLnRxvosctl2 = 0x00D800B4,\n-\tHwPfPcieLnRxlosctl = 0x00D800B8,\n-\tHwPfPcieLnRxlos = 0x00D800BC,\n-\tHwPfPcieLnRxlosvval = 0x00D800C0,\n-\tHwPfPcieLnRxvosd0 = 0x00D800C4,\n-\tHwPfPcieLnRxvosd1 = 0x00D800C8,\n-\tHwPfPcieLnRxvosep0 = 0x00D800CC,\n-\tHwPfPcieLnRxvosep1 = 0x00D800D0,\n-\tHwPfPcieLnRxvosen0 = 0x00D800D4,\n-\tHwPfPcieLnRxvosen1 = 0x00D800D8,\n-\tHwPfPcieLnRxvosafe = 0x00D800DC,\n-\tHwPfPcieLnRxvosa0 = 0x00D800E0,\n-\tHwPfPcieLnRxvosa0Out = 0x00D800E4,\n-\tHwPfPcieLnRxvosa1 = 0x00D800E8,\n-\tHwPfPcieLnRxvosa1Out = 0x00D800EC,\n-\tHwPfPcieLnRxmisc = 0x00D800F0,\n-\tHwPfPcieLnRxbeacon = 0x00D800F4,\n-\tHwPfPcieLnRxdssout = 0x00D800F8,\n-\tHwPfPcieLnRxdssout2 = 0x00D800FC,\n-\tHwPfPcieLnAlphapctrl = 0x00D80100,\n-\tHwPfPcieLnAlphanctrl = 0x00D80104,\n \tHwPfPcieLnAdaptctrl = 0x00D80108,\n-\tHwPfPcieLnAdaptctrl1 = 0x00D8010C,\n-\tHwPfPcieLnAdaptstatus = 0x00D80110,\n-\tHwPfPcieLnAdaptvga1 = 0x00D80114,\n-\tHwPfPcieLnAdaptvga2 = 0x00D80118,\n-\tHwPfPcieLnAdaptvga3 = 0x00D8011C,\n-\tHwPfPcieLnAdaptvga4 = 0x00D80120,\n-\tHwPfPcieLnAdaptboost1 = 0x00D80124,\n-\tHwPfPcieLnAdaptboost2 = 0x00D80128,\n-\tHwPfPcieLnAdaptboost3 = 0x00D8012C,\n-\tHwPfPcieLnAdaptboost4 = 0x00D80130,\n-\tHwPfPcieLnAdaptsslms1 = 0x00D80134,\n-\tHwPfPcieLnAdaptsslms2 = 0x00D80138,\n-\tHwPfPcieLnAdaptvgaStatus = 0x00D8013C,\n-\tHwPfPcieLnAdaptboostStatus = 0x00D80140,\n-\tHwPfPcieLnAdaptsslmsStatus1 = 0x00D80144,\n-\tHwPfPcieLnAdaptsslmsStatus2 = 0x00D80148,\n-\tHwPfPcieLnAfectrl1 = 0x00D8014C,\n-\tHwPfPcieLnAfectrl2 = 0x00D80150,\n-\tHwPfPcieLnAfectrl3 = 0x00D80154,\n-\tHwPfPcieLnAfedefault1 = 0x00D80158,\n-\tHwPfPcieLnAfedefault2 = 0x00D8015C,\n-\tHwPfPcieLnDfectrl1 = 0x00D80160,\n-\tHwPfPcieLnDfectrl2 = 0x00D80164,\n-\tHwPfPcieLnDfectrl3 = 0x00D80168,\n-\tHwPfPcieLnDfectrl4 = 0x00D8016C,\n-\tHwPfPcieLnDfectrl5 = 0x00D80170,\n-\tHwPfPcieLnDfectrl6 = 0x00D80174,\n-\tHwPfPcieLnAfestatus1 = 0x00D80178,\n-\tHwPfPcieLnAfestatus2 = 0x00D8017C,\n-\tHwPfPcieLnDfestatus1 = 0x00D80180,\n-\tHwPfPcieLnDfestatus2 = 0x00D80184,\n-\tHwPfPcieLnDfestatus3 = 0x00D80188,\n-\tHwPfPcieLnDfestatus4 = 0x00D8018C,\n-\tHwPfPcieLnDfestatus5 = 0x00D80190,\n-\tHwPfPcieLnAlphastatus = 0x00D80194,\n-\tHwPfPcieLnFomctrl1 = 0x00D80198,\n-\tHwPfPcieLnFomctrl2 = 0x00D8019C,\n-\tHwPfPcieLnFomctrl3 = 0x00D801A0,\n-\tHwPfPcieLnAclkcalStatus = 0x00D801A4,\n-\tHwPfPcieLnOffscorrStatus = 0x00D801A8,\n-\tHwPfPcieLnEyewidthStatus = 0x00D801AC,\n-\tHwPfPcieLnEyeheightStatus = 0x00D801B0,\n-\tHwPfPcieLnAsicTxovr1 = 0x00D801B4,\n-\tHwPfPcieLnAsicTxovr2 = 0x00D801B8,\n-\tHwPfPcieLnAsicTxovr3 = 0x00D801BC,\n-\tHwPfPcieLnTxbiasadjOvr = 0x00D801C0,\n-\tHwPfPcieLnTxcsr = 0x00D801C4,\n-\tHwPfPcieLnTxtest = 0x00D801C8,\n-\tHwPfPcieLnTxtestword = 0x00D801CC,\n-\tHwPfPcieLnTxtestwordHigh = 0x00D801D0,\n-\tHwPfPcieLnTxdrive = 0x00D801D4,\n-\tHwPfPcieLnMtcsLn = 0x00D801D8,\n-\tHwPfPcieLnStatsumLn = 0x00D801DC,\n-\tHwPfPcieLnRcbusScratch = 0x00D801E0,\n-\tHwPfPcieLnRcbusMinorrev = 0x00D801F0,\n-\tHwPfPcieLnRcbusMajorrev = 0x00D801F4,\n-\tHwPfPcieLnRcbusBlocktype = 0x00D801F8,\n-\tHwPfPcieSupPllcsr = 0x00D80800,\n-\tHwPfPcieSupPlldiv = 0x00D80804,\n-\tHwPfPcieSupPllcal = 0x00D80808,\n-\tHwPfPcieSupPllcalsts = 0x00D8080C,\n-\tHwPfPcieSupPllmeas = 0x00D80810,\n-\tHwPfPcieSupPlldactrim = 0x00D80814,\n-\tHwPfPcieSupPllbiastrim = 0x00D80818,\n-\tHwPfPcieSupPllbwtrim = 0x00D8081C,\n-\tHwPfPcieSupPllcaldly = 0x00D80820,\n-\tHwPfPcieSupRefclkonpclkctrl = 0x00D80824,\n-\tHwPfPcieSupPclkdelay = 0x00D80828,\n-\tHwPfPcieSupPhyconfig = 0x00D8082C,\n-\tHwPfPcieSupRcalIntf = 0x00D80830,\n-\tHwPfPcieSupAuxcsr = 0x00D80834,\n-\tHwPfPcieSupVref = 0x00D80838,\n-\tHwPfPcieSupLinkmode = 0x00D8083C,\n-\tHwPfPcieSupRrefcalctl = 0x00D80840,\n-\tHwPfPcieSupRrefcal = 0x00D80844,\n-\tHwPfPcieSupRrefcaldly = 0x00D80848,\n-\tHwPfPcieSupTximpcalctl = 0x00D8084C,\n-\tHwPfPcieSupTximpcal = 0x00D80850,\n-\tHwPfPcieSupTximpoffset = 0x00D80854,\n-\tHwPfPcieSupTximpcaldly = 0x00D80858,\n-\tHwPfPcieSupRximpcalctl = 0x00D8085C,\n-\tHwPfPcieSupRximpcal = 0x00D80860,\n-\tHwPfPcieSupRximpoffset = 0x00D80864,\n-\tHwPfPcieSupRximpcaldly = 0x00D80868,\n-\tHwPfPcieSupFence = 0x00D8086C,\n-\tHwPfPcieSupMtcs = 0x00D80870,\n-\tHwPfPcieSupStatsum = 0x00D809B8,\n-\tHwPfPciePcsDpStatus0 = 0x00D81000,\n-\tHwPfPciePcsDpControl0 = 0x00D81004,\n-\tHwPfPciePcsPmaStatusLane0 = 0x00D81008,\n-\tHwPfPciePcsPipeStatusLane0 = 0x00D8100C,\n-\tHwPfPciePcsTxdeemph0Lane0 = 0x00D81010,\n-\tHwPfPciePcsTxdeemph1Lane0 = 0x00D81014,\n-\tHwPfPciePcsInternalStatusLane0 = 0x00D81018,\n-\tHwPfPciePcsDpStatus1 = 0x00D8101C,\n-\tHwPfPciePcsDpControl1 = 0x00D81020,\n-\tHwPfPciePcsPmaStatusLane1 = 0x00D81024,\n-\tHwPfPciePcsPipeStatusLane1 = 0x00D81028,\n-\tHwPfPciePcsTxdeemph0Lane1 = 0x00D8102C,\n-\tHwPfPciePcsTxdeemph1Lane1 = 0x00D81030,\n-\tHwPfPciePcsInternalStatusLane1 = 0x00D81034,\n-\tHwPfPciePcsDpStatus2 = 0x00D81038,\n-\tHwPfPciePcsDpControl2 = 0x00D8103C,\n-\tHwPfPciePcsPmaStatusLane2 = 0x00D81040,\n-\tHwPfPciePcsPipeStatusLane2 = 0x00D81044,\n-\tHwPfPciePcsTxdeemph0Lane2 = 0x00D81048,\n-\tHwPfPciePcsTxdeemph1Lane2 = 0x00D8104C,\n-\tHwPfPciePcsInternalStatusLane2 = 0x00D81050,\n-\tHwPfPciePcsDpStatus3 = 0x00D81054,\n-\tHwPfPciePcsDpControl3 = 0x00D81058,\n-\tHwPfPciePcsPmaStatusLane3 = 0x00D8105C,\n-\tHwPfPciePcsPipeStatusLane3 = 0x00D81060,\n-\tHwPfPciePcsTxdeemph0Lane3 = 0x00D81064,\n-\tHwPfPciePcsTxdeemph1Lane3 = 0x00D81068,\n-\tHwPfPciePcsInternalStatusLane3 = 0x00D8106C,\n-\tHwPfPciePcsEbStatus0 = 0x00D81070,\n-\tHwPfPciePcsEbStatus1 = 0x00D81074,\n-\tHwPfPciePcsEbStatus2 = 0x00D81078,\n-\tHwPfPciePcsEbStatus3 = 0x00D8107C,\n-\tHwPfPciePcsPllSettingPcieG1 = 0x00D81088,\n-\tHwPfPciePcsPllSettingPcieG2 = 0x00D8108C,\n-\tHwPfPciePcsPllSettingPcieG3 = 0x00D81090,\n-\tHwPfPciePcsControl = 0x00D81094,\n \tHwPfPciePcsEqControl = 0x00D81098,\n-\tHwPfPciePcsEqTimer = 0x00D8109C,\n-\tHwPfPciePcsEqErrStatus = 0x00D810A0,\n-\tHwPfPciePcsEqErrCount = 0x00D810A4,\n-\tHwPfPciePcsStatus = 0x00D810A8,\n-\tHwPfPciePcsMiscRegister = 0x00D810AC,\n-\tHwPfPciePcsObsControl = 0x00D810B0,\n-\tHwPfPciePcsPrbsCount0 = 0x00D81200,\n-\tHwPfPciePcsBistControl0 = 0x00D81204,\n-\tHwPfPciePcsBistStaticWord00 = 0x00D81208,\n-\tHwPfPciePcsBistStaticWord10 = 0x00D8120C,\n-\tHwPfPciePcsBistStaticWord20 = 0x00D81210,\n-\tHwPfPciePcsBistStaticWord30 = 0x00D81214,\n-\tHwPfPciePcsPrbsCount1 = 0x00D81220,\n-\tHwPfPciePcsBistControl1 = 0x00D81224,\n-\tHwPfPciePcsBistStaticWord01 = 0x00D81228,\n-\tHwPfPciePcsBistStaticWord11 = 0x00D8122C,\n-\tHwPfPciePcsBistStaticWord21 = 0x00D81230,\n-\tHwPfPciePcsBistStaticWord31 = 0x00D81234,\n-\tHwPfPciePcsPrbsCount2 = 0x00D81240,\n-\tHwPfPciePcsBistControl2 = 0x00D81244,\n-\tHwPfPciePcsBistStaticWord02 = 0x00D81248,\n-\tHwPfPciePcsBistStaticWord12 = 0x00D8124C,\n-\tHwPfPciePcsBistStaticWord22 = 0x00D81250,\n-\tHwPfPciePcsBistStaticWord32 = 0x00D81254,\n-\tHwPfPciePcsPrbsCount3 = 0x00D81260,\n-\tHwPfPciePcsBistControl3 = 0x00D81264,\n-\tHwPfPciePcsBistStaticWord03 = 0x00D81268,\n-\tHwPfPciePcsBistStaticWord13 = 0x00D8126C,\n-\tHwPfPciePcsBistStaticWord23 = 0x00D81270,\n-\tHwPfPciePcsBistStaticWord33 = 0x00D81274,\n-\tHwPfPcieGpexLtssmStateCntrl = 0x00D90400,\n-\tHwPfPcieGpexLtssmStateStatus = 0x00D90404,\n-\tHwPfPcieGpexSkipFreqTimer = 0x00D90408,\n-\tHwPfPcieGpexLaneSelect = 0x00D9040C,\n-\tHwPfPcieGpexLaneDeskew = 0x00D90410,\n-\tHwPfPcieGpexRxErrorStatus = 0x00D90414,\n-\tHwPfPcieGpexLaneNumControl = 0x00D90418,\n-\tHwPfPcieGpexNFstControl = 0x00D9041C,\n-\tHwPfPcieGpexLinkStatus = 0x00D90420,\n-\tHwPfPcieGpexAckReplayTimeout = 0x00D90438,\n-\tHwPfPcieGpexSeqNumberStatus = 0x00D9043C,\n-\tHwPfPcieGpexCoreClkRatio = 0x00D90440,\n-\tHwPfPcieGpexDllTholdControl = 0x00D90448,\n-\tHwPfPcieGpexPmTimer = 0x00D90450,\n-\tHwPfPcieGpexPmeTimeout = 0x00D90454,\n-\tHwPfPcieGpexAspmL1Timer = 0x00D90458,\n-\tHwPfPcieGpexAspmReqTimer = 0x00D9045C,\n-\tHwPfPcieGpexAspmL1Dis = 0x00D90460,\n-\tHwPfPcieGpexAdvisoryErrorControl = 0x00D90468,\n-\tHwPfPcieGpexId = 0x00D90470,\n-\tHwPfPcieGpexClasscode = 0x00D90474,\n-\tHwPfPcieGpexSubsystemId = 0x00D90478,\n-\tHwPfPcieGpexDeviceCapabilities = 0x00D9047C,\n-\tHwPfPcieGpexLinkCapabilities = 0x00D90480,\n-\tHwPfPcieGpexFunctionNumber = 0x00D90484,\n-\tHwPfPcieGpexPmCapabilities = 0x00D90488,\n-\tHwPfPcieGpexFunctionSelect = 0x00D9048C,\n-\tHwPfPcieGpexErrorCounter = 0x00D904AC,\n-\tHwPfPcieGpexConfigReady = 0x00D904B0,\n-\tHwPfPcieGpexFcUpdateTimeout = 0x00D904B8,\n-\tHwPfPcieGpexFcUpdateTimer = 0x00D904BC,\n-\tHwPfPcieGpexVcBufferLoad = 0x00D904C8,\n-\tHwPfPcieGpexVcBufferSizeThold = 0x00D904CC,\n-\tHwPfPcieGpexVcBufferSelect = 0x00D904D0,\n-\tHwPfPcieGpexBarEnable = 0x00D904D4,\n-\tHwPfPcieGpexBarDwordLower = 0x00D904D8,\n-\tHwPfPcieGpexBarDwordUpper = 0x00D904DC,\n-\tHwPfPcieGpexBarSelect = 0x00D904E0,\n-\tHwPfPcieGpexCreditCounterSelect = 0x00D904E4,\n-\tHwPfPcieGpexCreditCounterStatus = 0x00D904E8,\n-\tHwPfPcieGpexTlpHeaderSelect = 0x00D904EC,\n-\tHwPfPcieGpexTlpHeaderDword0 = 0x00D904F0,\n-\tHwPfPcieGpexTlpHeaderDword1 = 0x00D904F4,\n-\tHwPfPcieGpexTlpHeaderDword2 = 0x00D904F8,\n-\tHwPfPcieGpexTlpHeaderDword3 = 0x00D904FC,\n-\tHwPfPcieGpexRelaxOrderControl = 0x00D90500,\n-\tHwPfPcieGpexBarPrefetch = 0x00D90504,\n-\tHwPfPcieGpexFcCheckControl = 0x00D90508,\n-\tHwPfPcieGpexFcUpdateTimerTraffic = 0x00D90518,\n-\tHwPfPcieGpexPhyControl0 = 0x00D9053C,\n-\tHwPfPcieGpexPhyControl1 = 0x00D90544,\n-\tHwPfPcieGpexPhyControl2 = 0x00D9054C,\n-\tHwPfPcieGpexUserControl0 = 0x00D9055C,\n-\tHwPfPcieGpexUncorrErrorStatus = 0x00D905F0,\n-\tHwPfPcieGpexRxCplError = 0x00D90620,\n-\tHwPfPcieGpexRxCplErrorDword0 = 0x00D90624,\n-\tHwPfPcieGpexRxCplErrorDword1 = 0x00D90628,\n-\tHwPfPcieGpexRxCplErrorDword2 = 0x00D9062C,\n-\tHwPfPcieGpexPabSwResetEn = 0x00D90630,\n-\tHwPfPcieGpexGen3Control0 = 0x00D90634,\n-\tHwPfPcieGpexGen3Control1 = 0x00D90638,\n-\tHwPfPcieGpexGen3Control2 = 0x00D9063C,\n-\tHwPfPcieGpexGen2ControlCsr = 0x00D90640,\n-\tHwPfPcieGpexTotalVfInitialVf0 = 0x00D90644,\n-\tHwPfPcieGpexTotalVfInitialVf1 = 0x00D90648,\n-\tHwPfPcieGpexSriovLinkDevId0 = 0x00D90684,\n-\tHwPfPcieGpexSriovLinkDevId1 = 0x00D90688,\n-\tHwPfPcieGpexSriovPageSize0 = 0x00D906C4,\n-\tHwPfPcieGpexSriovPageSize1 = 0x00D906C8,\n-\tHwPfPcieGpexIdVersion = 0x00D906FC,\n-\tHwPfPcieGpexSriovVfOffsetStride0 = 0x00D90704,\n-\tHwPfPcieGpexSriovVfOffsetStride1 = 0x00D90708,\n-\tHwPfPcieGpexGen3DeskewControl = 0x00D907B4,\n-\tHwPfPcieGpexGen3EqControl = 0x00D907B8,\n-\tHwPfPcieGpexBridgeVersion = 0x00D90800,\n-\tHwPfPcieGpexBridgeCapability = 0x00D90804,\n \tHwPfPcieGpexBridgeControl = 0x00D90808,\n-\tHwPfPcieGpexBridgeStatus = 0x00D9080C,\n-\tHwPfPcieGpexEngineActivityStatus = 0x00D9081C,\n-\tHwPfPcieGpexEngineResetControl = 0x00D90820,\n \tHwPfPcieGpexAxiPioControl = 0x00D90840,\n-\tHwPfPcieGpexAxiPioStatus = 0x00D90844,\n-\tHwPfPcieGpexAmbaSlaveCmdStatus = 0x00D90848,\n-\tHwPfPcieGpexPexPioControl = 0x00D908C0,\n-\tHwPfPcieGpexPexPioStatus = 0x00D908C4,\n-\tHwPfPcieGpexAmbaMasterStatus = 0x00D908C8,\n-\tHwPfPcieGpexCsrSlaveCmdStatus = 0x00D90920,\n-\tHwPfPcieGpexMailboxAxiControl = 0x00D90A50,\n-\tHwPfPcieGpexMailboxAxiData = 0x00D90A54,\n-\tHwPfPcieGpexMailboxPexControl = 0x00D90A90,\n-\tHwPfPcieGpexMailboxPexData = 0x00D90A94,\n-\tHwPfPcieGpexPexInterruptEnable = 0x00D90AD0,\n-\tHwPfPcieGpexPexInterruptStatus = 0x00D90AD4,\n-\tHwPfPcieGpexPexInterruptAxiPioVector = 0x00D90AD8,\n-\tHwPfPcieGpexPexInterruptPexPioVector = 0x00D90AE0,\n-\tHwPfPcieGpexPexInterruptMiscVector = 0x00D90AF8,\n-\tHwPfPcieGpexAmbaInterruptPioEnable = 0x00D90B00,\n-\tHwPfPcieGpexAmbaInterruptMiscEnable = 0x00D90B0C,\n-\tHwPfPcieGpexAmbaInterruptPioStatus = 0x00D90B10,\n-\tHwPfPcieGpexAmbaInterruptMiscStatus = 0x00D90B1C,\n-\tHwPfPcieGpexPexPmControl = 0x00D90B80,\n-\tHwPfPcieGpexSlotMisc = 0x00D90B88,\n-\tHwPfPcieGpexAxiAddrMappingControl = 0x00D90BA0,\n-\tHwPfPcieGpexAxiAddrMappingWindowAxiBase = 0x00D90BA4,\n-\tHwPfPcieGpexAxiAddrMappingWindowPexBaseLow = 0x00D90BA8,\n \tHwPfPcieGpexAxiAddrMappingWindowPexBaseHigh = 0x00D90BAC,\n-\tHwPfPcieGpexPexBarAddrFunc0Bar0 = 0x00D91BA0,\n-\tHwPfPcieGpexPexBarAddrFunc0Bar1 = 0x00D91BA4,\n-\tHwPfPcieGpexAxiAddrMappingPcieHdrParam = 0x00D95BA0,\n-\tHwPfPcieGpexExtAxiAddrMappingAxiBase = 0x00D980A0,\n-\tHwPfPcieGpexPexExtBarAddrFunc0Bar0 = 0x00D984A0,\n-\tHwPfPcieGpexPexExtBarAddrFunc0Bar1 = 0x00D984A4,\n-\tHwPfPcieGpexAmbaInterruptFlrEnable = 0x00D9B960,\n-\tHwPfPcieGpexAmbaInterruptFlrStatus = 0x00D9B9A0,\n-\tHwPfPcieGpexExtAxiAddrMappingSize = 0x00D9BAF0,\n-\tHwPfPcieGpexPexPioAwcacheControl = 0x00D9C300,\n-\tHwPfPcieGpexPexPioArcacheControl = 0x00D9C304,\n-\tHwPfPcieGpexPabObSizeControlVc0 = 0x00D9C310\n };\n \n /* TIP PF Interrupt numbers */\n", "prefixes": [ "v9", "01/14" ] }