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GET /api/patches/117211/?format=api
{ "id": 117211, "url": "http://patches.dpdk.org/api/patches/117211/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220930125315.5079-2-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220930125315.5079-2-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220930125315.5079-2-suanmingm@nvidia.com", "date": "2022-09-30T12:52:59", "name": "[v3,01/17] net/mlx5: fix invalid flow attributes", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "15b9a412b81b5fb76639bab251dd88e8c159826f", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220930125315.5079-2-suanmingm@nvidia.com/mbox/", "series": [ { "id": 24935, "url": "http://patches.dpdk.org/api/series/24935/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24935", "date": "2022-09-30T12:52:58", "name": "net/mlx5: HW steering PMD update", "version": 3, "mbox": "http://patches.dpdk.org/series/24935/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/117211/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/117211/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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net/mlx5: fix invalid flow attributes", "Date": "Fri, 30 Sep 2022 15:52:59 +0300", "Message-ID": "<20220930125315.5079-2-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220930125315.5079-1-suanmingm@nvidia.com>", "References": "<20220923144334.27736-1-suanmingm@nvidia.com>\n <20220930125315.5079-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT031:EE_|CY8PR12MB7361:EE_", "X-MS-Office365-Filtering-Correlation-Id": "66939b0e-a08b-47ae-2082-08daa2e2c9a9", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n dA1ZiYsVe44JRwNfYiTKepkuPkVhefL6dx42MFSJchsQXDljHaM3etzfj+/WYqna56ixGA19D1UpOxKN4T6yi68XfvPYhT7X5ve//VHjJVHtYcwaYF0k1lojTKTKU+NR7zWSF54lKRmnVCdAGi61NCU4KoE2sO7MulxIDIcSLwerkGUDCFsciMQC3GvOSGdJRrWsa4h466UJxQIr6pHJwobJpd0+5SVGh9BK9ODCeTW+f5jR4JMffe/ozbV4SOrRN6oUz9kqQjNTrmlJebstiMybUl3dnrnsl3zaYvNsjoItXLteEErT7uDkhq5lFDWxoWthrV+hc11uhWVuEgtAf9YnCB6Htkf71P0fH+zYpYpDDF+o3ny6BE67RKmXlvO66RABGfPGc1LzhNKdREd2ebhPKJHmTfb46deUEtQ7vCgVQ9dzRZKE9+QUPPKjVOJIReVQhmg0Ji82R3SRI3FwcU0H20FB7u35uYVDY820LCIrTiulygY6m/m9NOOq8ak8HaPmQnYcREGxHdVtMqtG9NVITVuqRvWb7Z1//eGGgprymk7Vf9zDgder55iZQKHUCVvM55CtQ79s6j5oPlPSWi7esXCaVwYrCUjSIWIS8pkjxYfuwrvsj9JGMeCfu8UuEXNO7fQJ9fyPIJc+VV5YiKI+rnfGgIaM8/VJp39mJ5m2iozv27xui7hbTtWicqk16yBqs8YCKheKre71xRji+OQqJL5oEmsqaCoo/tQjZFMqQPX6s03yQfca6fCGcFZI8Fl+rx7mIDJhOKfPMJz17Q==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(396003)(136003)(39860400002)(376002)(346002)(451199015)(46966006)(36840700001)(40470700004)(7636003)(1076003)(2616005)(2906002)(186003)(16526019)(336012)(82740400003)(70586007)(70206006)(4326008)(8676002)(41300700001)(6666004)(107886003)(478600001)(6636002)(316002)(86362001)(110136005)(55016003)(40460700003)(36756003)(40480700001)(7696005)(6286002)(26005)(82310400005)(8936002)(5660300002)(54906003)(356005)(47076005)(426003)(36860700001)(83380400001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Sep 2022 12:53:35.4553 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 66939b0e-a08b-47ae-2082-08daa2e2c9a9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT031.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY8PR12MB7361", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "In the function flow_get_drv_type(), attr will be read in non-HWS mode.\nIn case user call the HWS API in SWS mode, attr should be placed in\nHWS functions, or it will cause crash.\n\nFixes: 572801ab860f (\"ethdev: backport upstream rte_flow_async codes\")\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.c | 38 ++++++++++++++++++++++++------------\n 1 file changed, 26 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 45109001ca..3abb39aa92 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -3740,6 +3740,8 @@ flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr)\n \t */\n \tif (priv->sh->config.dv_flow_en == 2)\n \t\treturn MLX5_FLOW_TYPE_HW;\n+\tif (!attr)\n+\t\treturn MLX5_FLOW_TYPE_MIN;\n \t/* If no OS specific type - continue with DV/VERBS selection */\n \tif (attr->transfer && priv->sh->config.dv_esw_en)\n \t\ttype = MLX5_FLOW_TYPE_DV;\n@@ -8252,8 +8254,9 @@ mlx5_flow_info_get(struct rte_eth_dev *dev,\n \t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8287,8 +8290,9 @@ mlx5_flow_port_configure(struct rte_eth_dev *dev,\n \t\t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8319,8 +8323,9 @@ mlx5_flow_pattern_template_create(struct rte_eth_dev *dev,\n \t\tstruct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr fattr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) {\n+\tif (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) {\n \t\trte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8350,8 +8355,9 @@ mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev,\n \t\t\t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8385,8 +8391,9 @@ mlx5_flow_actions_template_create(struct rte_eth_dev *dev,\n \t\t\tstruct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr fattr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) {\n+\tif (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) {\n \t\trte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8416,8 +8423,9 @@ mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev,\n \t\t\t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8457,8 +8465,9 @@ mlx5_flow_table_create(struct rte_eth_dev *dev,\n \t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr fattr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) {\n+\tif (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) {\n \t\trte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8494,8 +8503,9 @@ mlx5_flow_table_destroy(struct rte_eth_dev *dev,\n \t\t\tstruct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8542,8 +8552,9 @@ mlx5_flow_async_flow_create(struct rte_eth_dev *dev,\n \t\t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr fattr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) {\n+\tif (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) {\n \t\trte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8585,8 +8596,9 @@ mlx5_flow_async_flow_destroy(struct rte_eth_dev *dev,\n \t\t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr fattr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8621,8 +8633,9 @@ mlx5_flow_pull(struct rte_eth_dev *dev,\n \t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8650,8 +8663,9 @@ mlx5_flow_push(struct rte_eth_dev *dev,\n \t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n", "prefixes": [ "v3", "01/17" ] }