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GET /api/patches/117001/?format=api
{ "id": 117001, "url": "http://patches.dpdk.org/api/patches/117001/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220928033130.9106-2-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220928033130.9106-2-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220928033130.9106-2-suanmingm@nvidia.com", "date": "2022-09-28T03:31:14", "name": "[v2,01/17] net/mlx5: fix invalid flow attributes", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "15b9a412b81b5fb76639bab251dd88e8c159826f", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220928033130.9106-2-suanmingm@nvidia.com/mbox/", "series": [ { "id": 24870, "url": "http://patches.dpdk.org/api/series/24870/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24870", "date": "2022-09-28T03:31:15", "name": "net/mlx5: HW steering PMD update", "version": 2, "mbox": "http://patches.dpdk.org/series/24870/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/117001/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/117001/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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net/mlx5: fix invalid flow attributes", "Date": "Wed, 28 Sep 2022 06:31:14 +0300", "Message-ID": "<20220928033130.9106-2-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220928033130.9106-1-suanmingm@nvidia.com>", "References": "<20220923144334.27736-1-suanmingm@nvidia.com>\n <20220928033130.9106-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT044:EE_|IA0PR12MB7673:EE_", "X-MS-Office365-Filtering-Correlation-Id": "83bb3bb1-7856-461c-0318-08daa1020229", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n KoLjPJejN3lmVMzIH7257dsrWG4Ez4aXRdD201jOPbLxFTHTIkao6+XEpGczZxmEQ7Pa9LhXmqNCLLQBkR+o0R7JUxHkP3y8c3Q5Du/Fm6r7rfYeZ5nPMT/mKGghheOCqMC62VweosMC1G1ByMHyn392W+GWJ9OJO2lhsfYP+7Hip9o7u1wmlnHcB/+dLNWo+vEVNGr06miSAADt0pkuF2c95mHjuC1wrYhxJD+/bK2sH5BZK8WPjCzAFZNElifEwq9hsour3Gg2n8/UrupQgL+HUnLNLcje2lU0+G2C0YRpPkfIYu4KDab0+A9F4f2q9+TegGoaS3VLciXgrrihrARN+nIbpcmLJOhi7ImjKjzALdkse4GtNyU/BjP0ZdahvIOttstCE+aPHhRxjzpvpzjZgGP4Gykc8YX8Qqb4EKKq7zzk0Fqi+3NS/B5WS6iTLigNzoYyHFVewmxrszx3bjVS9G4rPIe6rbo5B+jWitBiXeF9htYYr3hHSTu3Oai+oerv+Mz0O5019DKJNgJFswX92AX0g41Lc9k8nusN5IDjR9Z3E9yjt6OIvD7JiSdyCdeU2dHWt7TTO6TXsZP7/F2ptT0LOybyjZZQORtSc1bDoXCnoqoGmfj7acYpb4WKHonEVijpNkk1VDC56Z4h13kFuJhBWNOzU49FTJjPnFIMvNMlGihCiHa8y8eOICIl8s2ZsrZ7cQx2Pn8mRpQ7jk6e3QhDoVilWmZw0GYq1vbnqahPH4lvOszB7a+TFEwwbcgv5iEB3SErNaiHHXwkHA==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n 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DM6NAM11FT044.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA0PR12MB7673", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "In the function flow_get_drv_type(), attr will be read in non-HWS mode.\nIn case user call the HWS API in SWS mode, attr should be placed in\nHWS functions, or it will cause crash.\n\nFixes: 572801ab860f (\"ethdev: backport upstream rte_flow_async codes\")\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.c | 38 ++++++++++++++++++++++++------------\n 1 file changed, 26 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 45109001ca..3abb39aa92 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -3740,6 +3740,8 @@ flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr)\n \t */\n \tif (priv->sh->config.dv_flow_en == 2)\n \t\treturn MLX5_FLOW_TYPE_HW;\n+\tif (!attr)\n+\t\treturn MLX5_FLOW_TYPE_MIN;\n \t/* If no OS specific type - continue with DV/VERBS selection */\n \tif (attr->transfer && priv->sh->config.dv_esw_en)\n \t\ttype = MLX5_FLOW_TYPE_DV;\n@@ -8252,8 +8254,9 @@ mlx5_flow_info_get(struct rte_eth_dev *dev,\n \t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8287,8 +8290,9 @@ mlx5_flow_port_configure(struct rte_eth_dev *dev,\n \t\t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8319,8 +8323,9 @@ mlx5_flow_pattern_template_create(struct rte_eth_dev *dev,\n \t\tstruct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr fattr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) {\n+\tif (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) {\n \t\trte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8350,8 +8355,9 @@ mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev,\n \t\t\t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8385,8 +8391,9 @@ mlx5_flow_actions_template_create(struct rte_eth_dev *dev,\n \t\t\tstruct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr fattr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) {\n+\tif (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) {\n \t\trte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8416,8 +8423,9 @@ mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev,\n \t\t\t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8457,8 +8465,9 @@ mlx5_flow_table_create(struct rte_eth_dev *dev,\n \t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr fattr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) {\n+\tif (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) {\n \t\trte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8494,8 +8503,9 @@ mlx5_flow_table_destroy(struct rte_eth_dev *dev,\n \t\t\tstruct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8542,8 +8552,9 @@ mlx5_flow_async_flow_create(struct rte_eth_dev *dev,\n \t\t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr fattr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) {\n+\tif (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) {\n \t\trte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8585,8 +8596,9 @@ mlx5_flow_async_flow_destroy(struct rte_eth_dev *dev,\n \t\t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr fattr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8621,8 +8633,9 @@ mlx5_flow_pull(struct rte_eth_dev *dev,\n \t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n@@ -8650,8 +8663,9 @@ mlx5_flow_push(struct rte_eth_dev *dev,\n \t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_driver_ops *fops;\n+\tstruct rte_flow_attr attr = {0};\n \n-\tif (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW)\n+\tif (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n", "prefixes": [ "v2", "01/17" ] }