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GET /api/patches/116999/?format=api
{ "id": 116999, "url": "http://patches.dpdk.org/api/patches/116999/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220928033130.9106-3-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220928033130.9106-3-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220928033130.9106-3-suanmingm@nvidia.com", "date": "2022-09-28T03:31:15", "name": "[v2,02/17] net/mlx5: fix IPv6 and TCP RSS hash fields", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4412349130564eb21a110a4e817ef9f4c46d2c1e", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220928033130.9106-3-suanmingm@nvidia.com/mbox/", "series": [ { "id": 24870, "url": "http://patches.dpdk.org/api/series/24870/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24870", "date": "2022-09-28T03:31:15", "name": "net/mlx5: HW steering PMD update", "version": 2, "mbox": "http://patches.dpdk.org/series/24870/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/116999/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/116999/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 793ABA00C2;\n\tWed, 28 Sep 2022 05:32:04 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 284374113C;\n\tWed, 28 Sep 2022 05:32:04 +0200 (CEST)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2042.outbound.protection.outlook.com [40.107.243.42])\n by mails.dpdk.org (Postfix) with ESMTP id 9A06F41133\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, <orika@nvidia.com>", "Subject": "[PATCH v2 02/17] net/mlx5: fix IPv6 and TCP RSS hash fields", "Date": "Wed, 28 Sep 2022 06:31:15 +0300", "Message-ID": "<20220928033130.9106-3-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220928033130.9106-1-suanmingm@nvidia.com>", "References": "<20220923144334.27736-1-suanmingm@nvidia.com>\n <20220928033130.9106-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT098:EE_|CY5PR12MB6550:EE_", "X-MS-Office365-Filtering-Correlation-Id": "bb6db40d-b77b-4647-4271-08daa1020147", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n PhWmtHOq/2d7aU0WTcyAB8ZqD1gWgC+n+3fmC4eqfaPDQFGOBP5Utlj8HEXdaWQZjy6Bw7p+Bm6Q5gNs41CbZYsCvb2McrO+Zj0YNWvuSEx+uGTyyiJrwV0Il2mXxZAXp+JzEpEIikJ2sNDjZST7EiumR1lfC2IKsVRyxjWxdl3x+vhrJfCok11053BoBERnapWfmnMhAPgpsju3TQzoXCxLX06vf7Sdv/1z6xM2JLsMSd3Pj6IFLhmIlkCfXiCAWVsJn+JwKqTL53AFlCqT2Czv515hxF5x+6+r+xiKkLTaBiwXZJkj1wwgbOIn9iNmG/UFJb1tdnDUGePBFXfsPD1keVJ8YJNh3Cf7+iisY1N4xDd3JDGmnvzwpFeGtaCkB1cpM8Eoc+NbqX0S+EX36AjvHKlduPihZu8KwwMizFklOW5v6NgXxLRb0PuWgupkkgj+Q87IuR+53e7GrLYKNN1lrnbpaHUnofnGLSP6f/4NtGAFcSxwNeGK5cJa/ftoFw+avjRuq33n22FnI+fLVopGqS1qMTvVWEdjCngoZ18RMaxhC6FRzB6omtSOTLqNV79sRGu1oyQBVbr1UQCu3vhAZhFu+YqK1xhuaELytSwkTTwXFmdIDTW7aDmTrMmL9+ngngCHHcSi1pUd4eeCq7mcx9PrIOWdgqqJgj2vffPSUmB63S/PzNpbt+uDN05jdnioFlnz0IAkVk7StUCLFrWmJCTSbDE7XrCmNXXAkiJjXmMekAw/hLyoLWpdDbIAhGrLxEEv/WLQ+Dtc90UVWQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(346002)(376002)(39860400002)(136003)(396003)(451199015)(40470700004)(46966006)(36840700001)(6286002)(6636002)(356005)(4326008)(55016003)(26005)(40480700001)(54906003)(8676002)(7636003)(107886003)(70586007)(316002)(6666004)(47076005)(83380400001)(426003)(82310400005)(70206006)(110136005)(2616005)(82740400003)(7696005)(1076003)(336012)(36860700001)(478600001)(86362001)(36756003)(186003)(5660300002)(16526019)(8936002)(40460700003)(2906002)(41300700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Sep 2022 03:32:00.8237 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n bb6db40d-b77b-4647-4271-08daa1020147", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT098.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY5PR12MB6550", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "In the flow_dv_hashfields_set() function, while item_flags was 0,\nthe code went directly to the first if and the else case would\nnever have chance be checked. This caused the IPv6 and TCP hash\nfileds in the else case would never be set.\n\nThis commit adds the dedicate HW steering hash field set function\nto generate the RSS hash fields.\n\nFixes: 6540da0b93b5 (\"net/mlx5: fix RSS scaling issue\")\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_dv.c | 12 +++----\n drivers/net/mlx5/mlx5_flow_hw.c | 59 ++++++++++++++++++++++++++++++++-\n 2 files changed, 62 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex a4c59f3762..a9b0e84736 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -11302,8 +11302,7 @@ flow_dv_hashfields_set(uint64_t item_flags,\n \t\trss_inner = 1;\n #endif\n \tif ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||\n-\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4)) ||\n-\t !items) {\n+\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {\n \t\tif (rss_types & MLX5_IPV4_LAYER_TYPES) {\n \t\t\tif (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)\n \t\t\t\tfields |= IBV_RX_HASH_SRC_IPV4;\n@@ -11313,8 +11312,7 @@ flow_dv_hashfields_set(uint64_t item_flags,\n \t\t\t\tfields |= MLX5_IPV4_IBV_RX_HASH;\n \t\t}\n \t} else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||\n-\t\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6)) ||\n-\t\t !items) {\n+\t\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {\n \t\tif (rss_types & MLX5_IPV6_LAYER_TYPES) {\n \t\t\tif (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)\n \t\t\t\tfields |= IBV_RX_HASH_SRC_IPV6;\n@@ -11337,8 +11335,7 @@ flow_dv_hashfields_set(uint64_t item_flags,\n \t\treturn;\n \t}\n \tif ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||\n-\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP)) ||\n-\t !items) {\n+\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {\n \t\tif (rss_types & RTE_ETH_RSS_UDP) {\n \t\t\tif (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)\n \t\t\t\tfields |= IBV_RX_HASH_SRC_PORT_UDP;\n@@ -11348,8 +11345,7 @@ flow_dv_hashfields_set(uint64_t item_flags,\n \t\t\t\tfields |= MLX5_UDP_IBV_RX_HASH;\n \t\t}\n \t} else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||\n-\t\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP)) ||\n-\t\t !items) {\n+\t\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {\n \t\tif (rss_types & RTE_ETH_RSS_TCP) {\n \t\t\tif (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)\n \t\t\t\tfields |= IBV_RX_HASH_SRC_PORT_TCP;\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 7343d59f1f..46c4169b4f 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -62,6 +62,63 @@ flow_hw_rxq_flag_set(struct rte_eth_dev *dev, bool enable)\n \tpriv->mark_enabled = enable;\n }\n \n+/**\n+ * Set the hash fields according to the @p rss_desc information.\n+ *\n+ * @param[in] rss_desc\n+ * Pointer to the mlx5_flow_rss_desc.\n+ * @param[out] hash_fields\n+ * Pointer to the RSS hash fields.\n+ */\n+static void\n+flow_hw_hashfields_set(struct mlx5_flow_rss_desc *rss_desc,\n+\t\t uint64_t *hash_fields)\n+{\n+\tuint64_t fields = 0;\n+\tint rss_inner = 0;\n+\tuint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);\n+\n+#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n+\tif (rss_desc->level >= 2)\n+\t\trss_inner = 1;\n+#endif\n+\tif (rss_types & MLX5_IPV4_LAYER_TYPES) {\n+\t\tif (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_SRC_IPV4;\n+\t\telse if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_DST_IPV4;\n+\t\telse\n+\t\t\tfields |= MLX5_IPV4_IBV_RX_HASH;\n+\t} else if (rss_types & MLX5_IPV6_LAYER_TYPES) {\n+\t\tif (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_SRC_IPV6;\n+\t\telse if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_DST_IPV6;\n+\t\telse\n+\t\t\tfields |= MLX5_IPV6_IBV_RX_HASH;\n+\t}\n+\tif (rss_types & RTE_ETH_RSS_UDP) {\n+\t\tif (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_SRC_PORT_UDP;\n+\t\telse if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_DST_PORT_UDP;\n+\t\telse\n+\t\t\tfields |= MLX5_UDP_IBV_RX_HASH;\n+\t} else if (rss_types & RTE_ETH_RSS_TCP) {\n+\t\tif (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_SRC_PORT_TCP;\n+\t\telse if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_DST_PORT_TCP;\n+\t\telse\n+\t\t\tfields |= MLX5_TCP_IBV_RX_HASH;\n+\t}\n+\tif (rss_types & RTE_ETH_RSS_ESP)\n+\t\tfields |= IBV_RX_HASH_IPSEC_SPI;\n+\tif (rss_inner)\n+\t\tfields |= IBV_RX_HASH_INNER;\n+\t*hash_fields = fields;\n+}\n+\n /**\n * Generate the pattern item flags.\n * Will be used for shared RSS action.\n@@ -225,7 +282,7 @@ flow_hw_tir_action_register(struct rte_eth_dev *dev,\n \t\t MLX5_RSS_HASH_KEY_LEN);\n \t\trss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;\n \t\trss_desc.types = !rss->types ? RTE_ETH_RSS_IP : rss->types;\n-\t\tflow_dv_hashfields_set(0, &rss_desc, &rss_desc.hash_fields);\n+\t\tflow_hw_hashfields_set(&rss_desc, &rss_desc.hash_fields);\n \t\tflow_dv_action_rss_l34_hash_adjust(rss->types,\n \t\t\t\t\t\t &rss_desc.hash_fields);\n \t\tif (rss->level > 1) {\n", "prefixes": [ "v2", "02/17" ] }