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GET /api/patches/116973/?format=api
http://patches.dpdk.org/api/patches/116973/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220927150537.1464936-1-abdullah.sevincer@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220927150537.1464936-1-abdullah.sevincer@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220927150537.1464936-1-abdullah.sevincer@intel.com", "date": "2022-09-27T15:05:37", "name": "[v4] event/dlb2: fix max cq_depth/enq_depth cli override", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "141d6edf21d72dec960e3904107d539c3ab2db64", "submitter": { "id": 2843, "url": "http://patches.dpdk.org/api/people/2843/?format=api", "name": "Sevincer, Abdullah", "email": "abdullah.sevincer@intel.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220927150537.1464936-1-abdullah.sevincer@intel.com/mbox/", "series": [ { "id": 24866, "url": "http://patches.dpdk.org/api/series/24866/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24866", "date": "2022-09-27T15:05:37", "name": "[v4] event/dlb2: fix max cq_depth/enq_depth cli override", "version": 4, "mbox": "http://patches.dpdk.org/series/24866/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/116973/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/116973/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 75DBBA00C2;\n\tTue, 27 Sep 2022 17:05:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1364841133;\n\tTue, 27 Sep 2022 17:05:55 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 75DDB40694\n for <dev@dpdk.org>; Tue, 27 Sep 2022 17:05:52 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 Sep 2022 08:05:39 -0700", "from txanpdk02.an.intel.com ([10.123.117.76])\n by fmsmga005.fm.intel.com with ESMTP; 27 Sep 2022 08:05:39 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1664291152; x=1695827152;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=UW7bp9aOXi1sA2Fm1g6eDN0282FY1uZ8J1OmONDqv0s=;\n b=Z0pORPOrkr0PQooRpyy2EnRUDLMqYYi/m4GoqIiP9jJLFuVkPT5yRQLD\n tcmtPDPye7GBfUqPYOkTuqBYMtORoSsLqk6LMw6YgbNg2MyzZdLV0r09J\n fEFuLRyDzVoj8os/aFasF0VOHS75lB4KIzgYWW8pbDUpdo2SWeweoDyVn\n T5Q3b90bRHRJSWy7RPJG62OWRSXiU42Os3ZBs7y3C1/WJ66eecr+uBQ5U\n 5azcraMriphgiUhrI5NRAzT/eVwJ1BGW7HytGK+cuSAPctciJ+wFWmTow\n p5xSM6zhd9Flh2tISXWpeQax1ahCLbQfzb7Cu/8INAN4gjn/VgntRRou7 Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10483\"; a=\"327698185\"", "E=Sophos;i=\"5.93,349,1654585200\"; d=\"scan'208\";a=\"327698185\"", "E=McAfee;i=\"6500,9779,10483\"; a=\"950318675\"", "E=Sophos;i=\"5.93,349,1654585200\"; d=\"scan'208\";a=\"950318675\"" ], "X-ExtLoop1": "1", "From": "Abdullah Sevincer <abdullah.sevincer@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com,\n\tAbdullah Sevincer <abdullah.sevincer@intel.com>", "Subject": "[PATCH v4] event/dlb2: fix max cq_depth/enq_depth cli override", "Date": "Tue, 27 Sep 2022 10:05:37 -0500", "Message-Id": "<20220927150537.1464936-1-abdullah.sevincer@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220921162853.739427-1-abdullah.sevincer@intel.com>", "References": "<20220921162853.739427-1-abdullah.sevincer@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch addresses an issue of enqueuing more than\nmax_enq_depth and not able to dequeuing events equal\nto max_cq_depth in a single call of rte_event_enqueue_burst\nand rte_event_dequeue_burst.\n\nApply fix for restricting enqueue of events to max_enq_depth\nso that in a single rte_event_enqueue_burst() call at most\nmax_enq_depth events are enqueued.\n\nAlso set per port and domain history list sizes based on\ncq_depth. This results in dequeuing correct number of\nevents as set by max_cq_depth.\n\nSigned-off-by: Abdullah Sevincer <abdullah.sevincer@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 9 +++++----\n 1 file changed, 5 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 759578378f..dbb8284135 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -813,7 +813,7 @@ dlb2_hw_create_sched_domain(struct dlb2_eventdev *dlb2,\n \t\tcfg->num_ldb_queues;\n \n \tcfg->num_hist_list_entries = resources_asked->num_ldb_ports *\n-\t\tDLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;\n+\t\tevdev_dlb2_default_info.max_event_port_dequeue_depth;\n \n \tif (device_version == DLB2_HW_V2_5) {\n \t\tDLB2_LOG_DBG(\"sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, credits=%d\\n\",\n@@ -1538,7 +1538,7 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,\n \tcfg.cq_depth = rte_align32pow2(dequeue_depth);\n \tcfg.cq_depth_threshold = 1;\n \n-\tcfg.cq_history_list_size = DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;\n+\tcfg.cq_history_list_size = cfg.cq_depth;\n \n \tcfg.cos_id = ev_port->cos_id;\n \tcfg.cos_strict = 0;/* best effots */\n@@ -2966,6 +2966,7 @@ __dlb2_event_enqueue_burst(void *event_port,\n \tstruct dlb2_port *qm_port = &ev_port->qm_port;\n \tstruct process_local_port_data *port_data;\n \tint retries = ev_port->enq_retries;\n+\tint num_tx;\n \tint i;\n \n \tRTE_ASSERT(ev_port->enq_configured);\n@@ -2974,8 +2975,8 @@ __dlb2_event_enqueue_burst(void *event_port,\n \ti = 0;\n \n \tport_data = &dlb2_port[qm_port->id][PORT_TYPE(qm_port)];\n-\n-\twhile (i < num) {\n+\tnum_tx = RTE_MIN(num, ev_port->conf.enqueue_depth);\n+\twhile (i < num_tx) {\n \t\tuint8_t sched_types[DLB2_NUM_QES_PER_CACHE_LINE];\n \t\tuint8_t queue_ids[DLB2_NUM_QES_PER_CACHE_LINE];\n \t\tint pop_offs = 0;\n", "prefixes": [ "v4" ] }{ "id": 116973, "url": "