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GET /api/patches/116763/?format=api
{ "id": 116763, "url": "http://patches.dpdk.org/api/patches/116763/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220923144334.27736-25-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220923144334.27736-25-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220923144334.27736-25-suanmingm@nvidia.com", "date": "2022-09-23T14:43:31", "name": "[24/27] net/mlx5: add meter color flow matching in hws", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8550ebcb66934dd278d54fe237e1f2ee41bd6e4c", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220923144334.27736-25-suanmingm@nvidia.com/mbox/", "series": [ { "id": 24805, "url": "http://patches.dpdk.org/api/series/24805/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24805", "date": "2022-09-23T14:43:07", "name": "net/mlx5: HW steering PMD update", "version": 1, "mbox": "http://patches.dpdk.org/series/24805/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/116763/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/116763/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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net/mlx5: add meter color flow matching in hws", "Date": "Fri, 23 Sep 2022 17:43:31 +0300", "Message-ID": "<20220923144334.27736-25-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220923144334.27736-1-suanmingm@nvidia.com>", "References": "<20220923144334.27736-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT042:EE_|SN7PR12MB7321:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d92e94ce-ba43-4665-7ae0-08da9d722aff", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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SFS:(13230022)(4636009)(396003)(346002)(376002)(136003)(39860400002)(451199015)(40470700004)(46966006)(36840700001)(36756003)(47076005)(316002)(16526019)(54906003)(2616005)(6636002)(4326008)(356005)(82740400003)(1076003)(107886003)(26005)(86362001)(8936002)(426003)(6286002)(110136005)(186003)(336012)(40480700001)(7696005)(83380400001)(478600001)(8676002)(7636003)(2906002)(55016003)(36860700001)(70586007)(70206006)(41300700001)(5660300002)(40460700003)(82310400005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Sep 2022 14:44:49.8002 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d92e94ce-ba43-4665-7ae0-08da9d722aff", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT042.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB7321", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Alexander Kozyrev <akozyrev@nvidia.com>\n\nCreate hardware steering meter color support.\nAllow matching on a meter color using hardware steering.\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 1 +\n drivers/net/mlx5/mlx5_flow_dv.c | 32 ++++++++++++++++++++++++++++++--\n drivers/net/mlx5/mlx5_flow_hw.c | 12 ++++++++++++\n 3 files changed, 43 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 99d3c40f36..514903dbe1 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1526,6 +1526,7 @@ flow_hw_get_reg_id(enum rte_flow_item_type type, uint32_t id)\n \t\t */\n \t\treturn REG_A;\n \tcase RTE_FLOW_ITEM_TYPE_CONNTRACK:\n+\tcase RTE_FLOW_ITEM_TYPE_METER_COLOR:\n \t\treturn mlx5_flow_hw_aso_tag;\n \tcase RTE_FLOW_ITEM_TYPE_TAG:\n \t\tMLX5_ASSERT(id < MLX5_FLOW_HW_TAGS_MAX);\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex e1db68b532..0785734217 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -1387,6 +1387,7 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev,\n \t\treturn inherit < 0 ? 0 : inherit;\n \tcase RTE_FLOW_FIELD_IPV4_ECN:\n \tcase RTE_FLOW_FIELD_IPV6_ECN:\n+\tcase RTE_FLOW_FIELD_METER_COLOR\n \t\treturn 2;\n \tdefault:\n \t\tMLX5_ASSERT(false);\n@@ -1846,6 +1847,31 @@ mlx5_flow_field_id_to_modify_info\n \t\t\t\tinfo[idx].offset = data->offset;\n \t\t}\n \t\tbreak;\n+\tcase RTE_FLOW_FIELD_METER_COLOR:\n+\t\t{\n+\t\t\tconst uint32_t color_mask =\n+\t\t\t\t(UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;\n+\t\t\tint reg;\n+\n+\t\t\tif (priv->sh->config.dv_flow_en == 2)\n+\t\t\t\treg = flow_hw_get_reg_id\n+\t\t\t\t\t(RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);\n+\t\t\telse\n+\t\t\t\treg = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR,\n+\t\t\t\t\t\t 0, error);\n+\t\t\tif (reg < 0)\n+\t\t\t\treturn;\n+\t\t\tMLX5_ASSERT(reg != REG_NON);\n+\t\t\tMLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));\n+\t\t\tinfo[idx] = (struct field_modify_info){4, 0,\n+\t\t\t\t\t\treg_to_field[reg]};\n+\t\t\tif (mask)\n+\t\t\t\tmask[idx] = flow_modify_info_mask_32_masked\n+\t\t\t\t\t(width, data->offset, color_mask);\n+\t\t\telse\n+\t\t\t\tinfo[idx].offset = data->offset;\n+\t\t}\n+\t\tbreak;\n \tcase RTE_FLOW_FIELD_POINTER:\n \tcase RTE_FLOW_FIELD_VALUE:\n \tdefault:\n@@ -1893,7 +1919,7 @@ flow_dv_convert_action_modify_field\n \tuint32_t type, meta = 0;\n \n \tif (conf->src.field == RTE_FLOW_FIELD_POINTER ||\n-\t conf->src.field == RTE_FLOW_FIELD_VALUE) {\n+\t conf->src.field == RTE_FLOW_FIELD_VALUE) {/\n \t\ttype = MLX5_MODIFICATION_TYPE_SET;\n \t\t/** For SET fill the destination field (field) first. */\n \t\tmlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,\n@@ -1902,7 +1928,9 @@ flow_dv_convert_action_modify_field\n \t\titem.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?\n \t\t\t\t\t(void *)(uintptr_t)conf->src.pvalue :\n \t\t\t\t\t(void *)(uintptr_t)&conf->src.value;\n-\t\tif (conf->dst.field == RTE_FLOW_FIELD_META) {\n+\t\tif (conf->dst.field == RTE_FLOW_FIELD_META ||\n+\t\t conf->dst.field == RTE_FLOW_FIELD_TAG ||\n+\t\t conf->dst.field == RTE_FLOW_FIELD_METER_COLOR) {\n \t\t\tmeta = *(const unaligned_uint32_t *)item.spec;\n \t\t\tmeta = rte_cpu_to_be_32(meta);\n \t\t\titem.spec = &meta;\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 7e7b48f884..87b3e34cb4 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -870,6 +870,7 @@ flow_hw_modify_field_compile(struct rte_eth_dev *dev,\n \t\t\t\t(void *)(uintptr_t)&conf->src.value;\n \t\tif (conf->dst.field == RTE_FLOW_FIELD_META ||\n \t\t conf->dst.field == RTE_FLOW_FIELD_TAG ||\n+\t\t conf->dst.field == RTE_FLOW_FIELD_METER_COLOR ||\n \t\t conf->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {\n \t\t\tvalue = *(const unaligned_uint32_t *)item.spec;\n \t\t\tvalue = rte_cpu_to_be_32(value);\n@@ -1702,6 +1703,7 @@ flow_hw_modify_field_construct(struct mlx5_hw_q_job *job,\n \t\trte_memcpy(values, mhdr_action->src.pvalue, sizeof(values));\n \tif (mhdr_action->dst.field == RTE_FLOW_FIELD_META ||\n \t mhdr_action->dst.field == RTE_FLOW_FIELD_TAG ||\n+\t mhdr_action->dst.field == RTE_FLOW_FIELD_METER_COLOR ||\n \t mhdr_action->dst.field == (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) {\n \t\tvalue_p = (unaligned_uint32_t *)values;\n \t\t*value_p = rte_cpu_to_be_32(*value_p);\n@@ -3704,6 +3706,16 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\t\t\t\t\t\t\t \" attribute\");\n \t\t\t}\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_METER_COLOR:\n+\t\t{\n+\t\t\tint reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_METER_COLOR, 0);\n+\t\t\tif (reg == REG_NON)\n+\t\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t\t\t NULL,\n+\t\t\t\t\t\t\t \"Unsupported meter color register\");\n+\t\t\tbreak;\n+\t\t}\n \t\tcase RTE_FLOW_ITEM_TYPE_VOID:\n \t\tcase RTE_FLOW_ITEM_TYPE_ETH:\n \t\tcase RTE_FLOW_ITEM_TYPE_VLAN:\n", "prefixes": [ "24/27" ] }