Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 116726,
    "url": "http://patches.dpdk.org/api/patches/116726/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220923093829.3019525-3-junfeng.guo@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220923093829.3019525-3-junfeng.guo@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220923093829.3019525-3-junfeng.guo@intel.com",
    "date": "2022-09-23T09:38:22",
    "name": "[v3,2/9] net/gve: add logs and OS specific implementation",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "a48b96a316ed7bd776dc7f0f93290fe9b9fa80bc",
    "submitter": {
        "id": 1785,
        "url": "http://patches.dpdk.org/api/people/1785/?format=api",
        "name": "Junfeng Guo",
        "email": "junfeng.guo@intel.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220923093829.3019525-3-junfeng.guo@intel.com/mbox/",
    "series": [
        {
            "id": 24800,
            "url": "http://patches.dpdk.org/api/series/24800/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24800",
            "date": "2022-09-23T09:38:20",
            "name": "introduce GVE PMD",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/24800/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/116726/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/116726/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 40207A0544;\n\tFri, 23 Sep 2022 11:39:33 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6B14F42B8F;\n\tFri, 23 Sep 2022 11:39:25 +0200 (CEST)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 747244068E\n for <dev@dpdk.org>; Fri, 23 Sep 2022 11:39:22 +0200 (CEST)",
            "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 Sep 2022 02:39:15 -0700",
            "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by orsmga008.jf.intel.com with ESMTP; 23 Sep 2022 02:39:13 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1663925962; x=1695461962;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=ZRuYcMjiYdQrW0/Q+TFpBSZxyvmzK6LMcdscDfBMF2A=;\n b=IF06GDbmBGUNve+65fYiWd74sOuEFEpxJbtjWegWCuR+tZJuDxv/O/dX\n 7Ymp8/qb4vxeu+jEwHVhNYdK6TKtYhFB3i2ohEwVUYs413VrDibHnkVGI\n pqqnz4DNVP58uqC2osUfSclZYLnuHTpJJ75z8g0uoEbkJG0QBK3KVcEar\n GUsb+quLbThdhojuc3Jq8BdagBv4fv5FY09WD2X5RIHkEkDbTija8y/q9\n zrccJd06SJvdzkQxct0DQj/VyPdrXTEOsOpw0sC+IQ2K8rvqY6m8XLW46\n k+QR0AA9/27ADJL0W7R6YHcykNua2jeHJ2ktBC6hh9WhCRskxZwdPuVab Q==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6500,9779,10478\"; a=\"326885883\"",
            "E=Sophos;i=\"5.93,337,1654585200\"; d=\"scan'208\";a=\"326885883\"",
            "E=Sophos;i=\"5.93,337,1654585200\"; d=\"scan'208\";a=\"650891156\""
        ],
        "X-ExtLoop1": "1",
        "From": "Junfeng Guo <junfeng.guo@intel.com>",
        "To": "qi.z.zhang@intel.com,\n\tjingjing.wu@intel.com",
        "Cc": "ferruh.yigit@xilinx.com, dev@dpdk.org, xiaoyun.li@intel.com,\n awogbemila@google.com, bruce.richardson@intel.com, xueqin.lin@intel.com,\n junfeng.guo@intel.com, Haiyue Wang <haiyue.wang@intel.com>",
        "Subject": "[PATCH v3 2/9] net/gve: add logs and OS specific implementation",
        "Date": "Fri, 23 Sep 2022 17:38:22 +0800",
        "Message-Id": "<20220923093829.3019525-3-junfeng.guo@intel.com>",
        "X-Mailer": "git-send-email 2.34.1",
        "In-Reply-To": "<20220923093829.3019525-1-junfeng.guo@intel.com>",
        "References": "<20220829084127.934183-11-junfeng.guo@intel.com>\n <20220923093829.3019525-1-junfeng.guo@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Add GVE PMD logs.\nAdd some MACRO definitions and memory operations which are specific\nfor DPDK.\n\nSigned-off-by: Haiyue Wang <haiyue.wang@intel.com>\nSigned-off-by: Xiaoyun Li <xiaoyun.li@intel.com>\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n drivers/net/gve/gve_adminq.h   |   2 +\n drivers/net/gve/gve_desc.h     |   2 +\n drivers/net/gve/gve_desc_dqo.h |   2 +\n drivers/net/gve/gve_logs.h     |  14 +++\n drivers/net/gve/gve_osdep.h    | 159 +++++++++++++++++++++++++++++++++\n drivers/net/gve/gve_register.h |   2 +\n 6 files changed, 181 insertions(+)\n create mode 100644 drivers/net/gve/gve_logs.h\n create mode 100644 drivers/net/gve/gve_osdep.h",
    "diff": "diff --git a/drivers/net/gve/gve_adminq.h b/drivers/net/gve/gve_adminq.h\nindex c7114cc883..cd496760ae 100644\n--- a/drivers/net/gve/gve_adminq.h\n+++ b/drivers/net/gve/gve_adminq.h\n@@ -8,6 +8,8 @@\n #ifndef _GVE_ADMINQ_H\n #define _GVE_ADMINQ_H\n \n+#include \"gve_osdep.h\"\n+\n /* Admin queue opcodes */\n enum gve_adminq_opcodes {\n \tGVE_ADMINQ_DESCRIBE_DEVICE\t\t= 0x1,\ndiff --git a/drivers/net/gve/gve_desc.h b/drivers/net/gve/gve_desc.h\nindex 358755b7e0..627b9120dc 100644\n--- a/drivers/net/gve/gve_desc.h\n+++ b/drivers/net/gve/gve_desc.h\n@@ -9,6 +9,8 @@\n #ifndef _GVE_DESC_H_\n #define _GVE_DESC_H_\n \n+#include \"gve_osdep.h\"\n+\n /* A note on seg_addrs\n  *\n  * Base addresses encoded in seg_addr are not assumed to be physical\ndiff --git a/drivers/net/gve/gve_desc_dqo.h b/drivers/net/gve/gve_desc_dqo.h\nindex 0d533abcd1..5031752b43 100644\n--- a/drivers/net/gve/gve_desc_dqo.h\n+++ b/drivers/net/gve/gve_desc_dqo.h\n@@ -9,6 +9,8 @@\n #ifndef _GVE_DESC_DQO_H_\n #define _GVE_DESC_DQO_H_\n \n+#include \"gve_osdep.h\"\n+\n #define GVE_TX_MAX_HDR_SIZE_DQO 255\n #define GVE_TX_MIN_TSO_MSS_DQO 88\n \ndiff --git a/drivers/net/gve/gve_logs.h b/drivers/net/gve/gve_logs.h\nnew file mode 100644\nindex 0000000000..0d02da46e1\n--- /dev/null\n+++ b/drivers/net/gve/gve_logs.h\n@@ -0,0 +1,14 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2022 Intel Corporation\n+ */\n+\n+#ifndef _GVE_LOGS_H_\n+#define _GVE_LOGS_H_\n+\n+extern int gve_logtype_driver;\n+\n+#define PMD_DRV_LOG(level, fmt, args...) \\\n+\trte_log(RTE_LOG_ ## level, gve_logtype_driver, \"%s(): \" fmt \"\\n\", \\\n+\t\t__func__, ## args)\n+\n+#endif\ndiff --git a/drivers/net/gve/gve_osdep.h b/drivers/net/gve/gve_osdep.h\nnew file mode 100644\nindex 0000000000..ba882038f5\n--- /dev/null\n+++ b/drivers/net/gve/gve_osdep.h\n@@ -0,0 +1,159 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2022 Intel Corporation\n+ */\n+\n+#ifndef _GVE_OSDEP_H_\n+#define _GVE_OSDEP_H_\n+\n+#include <string.h>\n+#include <stdint.h>\n+#include <stdio.h>\n+#include <stdarg.h>\n+#include <inttypes.h>\n+#include <stdbool.h>\n+\n+#include <rte_bitops.h>\n+#include <rte_byteorder.h>\n+#include <rte_common.h>\n+#include <rte_ether.h>\n+#include <rte_io.h>\n+#include <rte_log.h>\n+#include <rte_malloc.h>\n+#include <rte_memcpy.h>\n+#include <rte_memzone.h>\n+\n+#include \"gve_logs.h\"\n+\n+typedef uint8_t u8;\n+typedef uint16_t u16;\n+typedef uint32_t u32;\n+typedef uint64_t u64;\n+\n+typedef rte_be16_t __sum16;\n+\n+typedef rte_be16_t __be16;\n+typedef rte_be32_t __be32;\n+typedef rte_be64_t __be64;\n+\n+typedef rte_iova_t dma_addr_t;\n+\n+#define ETH_MIN_MTU\tRTE_ETHER_MIN_MTU\n+#define ETH_ALEN\tRTE_ETHER_ADDR_LEN\n+\n+#ifndef PAGE_SHIFT\n+#define PAGE_SHIFT\t12\n+#endif\n+#ifndef PAGE_SIZE\n+#define PAGE_SIZE\t(1UL << PAGE_SHIFT)\n+#endif\n+\n+#define BIT(nr)\t\tRTE_BIT32(nr)\n+\n+#define be16_to_cpu(x) rte_be_to_cpu_16(x)\n+#define be32_to_cpu(x) rte_be_to_cpu_32(x)\n+#define be64_to_cpu(x) rte_be_to_cpu_64(x)\n+\n+#define cpu_to_be16(x) rte_cpu_to_be_16(x)\n+#define cpu_to_be32(x) rte_cpu_to_be_32(x)\n+#define cpu_to_be64(x) rte_cpu_to_be_64(x)\n+\n+#define READ_ONCE32(x) rte_read32(&(x))\n+\n+#ifndef ____cacheline_aligned\n+#define ____cacheline_aligned\t__rte_cache_aligned\n+#endif\n+#ifndef __packed\n+#define __packed\t\t__rte_packed\n+#endif\n+#define __iomem\n+\n+#define msleep(ms)\t\trte_delay_ms(ms)\n+\n+/* These macros are used to generate compilation errors if a struct/union\n+ * is not exactly the correct length. It gives a divide by zero error if\n+ * the struct/union is not of the correct size, otherwise it creates an\n+ * enum that is never used.\n+ */\n+#define GVE_CHECK_STRUCT_LEN(n, X) enum gve_static_assert_enum_##X \\\n+\t{ gve_static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0) }\n+#define GVE_CHECK_UNION_LEN(n, X) enum gve_static_asset_enum_##X \\\n+\t{ gve_static_assert_##X = (n) / ((sizeof(union X) == (n)) ? 1 : 0) }\n+\n+static __rte_always_inline u8\n+readb(volatile void *addr)\n+{\n+\treturn rte_read8(addr);\n+}\n+\n+static __rte_always_inline void\n+writeb(u8 value, volatile void *addr)\n+{\n+\trte_write8(value, addr);\n+}\n+\n+static __rte_always_inline void\n+writel(u32 value, volatile void *addr)\n+{\n+\trte_write32(value, addr);\n+}\n+\n+static __rte_always_inline u32\n+ioread32be(const volatile void *addr)\n+{\n+\treturn rte_be_to_cpu_32(rte_read32(addr));\n+}\n+\n+static __rte_always_inline void\n+iowrite32be(u32 value, volatile void *addr)\n+{\n+\twritel(rte_cpu_to_be_32(value), addr);\n+}\n+\n+/* DMA memory allocation tracking */\n+struct gve_dma_mem {\n+\tvoid *va;\n+\trte_iova_t pa;\n+\tuint32_t size;\n+\tconst void *zone;\n+};\n+\n+static inline void *\n+gve_alloc_dma_mem(struct gve_dma_mem *mem, u64 size)\n+{\n+\tstatic uint16_t gve_dma_memzone_id;\n+\tconst struct rte_memzone *mz = NULL;\n+\tchar z_name[RTE_MEMZONE_NAMESIZE];\n+\n+\tif (!mem)\n+\t\treturn NULL;\n+\n+\tsnprintf(z_name, sizeof(z_name), \"gve_dma_%u\",\n+\t\t __atomic_fetch_add(&gve_dma_memzone_id, 1, __ATOMIC_RELAXED));\n+\tmz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY,\n+\t\t\t\t\t RTE_MEMZONE_IOVA_CONTIG,\n+\t\t\t\t\t PAGE_SIZE);\n+\tif (!mz)\n+\t\treturn NULL;\n+\n+\tmem->size = size;\n+\tmem->va = mz->addr;\n+\tmem->pa = mz->iova;\n+\tmem->zone = mz;\n+\tPMD_DRV_LOG(DEBUG, \"memzone %s is allocated\", mz->name);\n+\n+\treturn mem->va;\n+}\n+\n+static inline void\n+gve_free_dma_mem(struct gve_dma_mem *mem)\n+{\n+\tPMD_DRV_LOG(DEBUG, \"memzone %s to be freed\",\n+\t\t    ((const struct rte_memzone *)mem->zone)->name);\n+\n+\trte_memzone_free(mem->zone);\n+\tmem->zone = NULL;\n+\tmem->va = NULL;\n+\tmem->pa = 0;\n+}\n+\n+#endif /* _GVE_OSDEP_H_ */\ndiff --git a/drivers/net/gve/gve_register.h b/drivers/net/gve/gve_register.h\nindex b65f336be2..a599c1a08e 100644\n--- a/drivers/net/gve/gve_register.h\n+++ b/drivers/net/gve/gve_register.h\n@@ -7,6 +7,8 @@\n #ifndef _GVE_REGISTER_H_\n #define _GVE_REGISTER_H_\n \n+#include \"gve_osdep.h\"\n+\n /* Fixed Configuration Registers */\n struct gve_registers {\n \t__be32\tdevice_status;\n",
    "prefixes": [
        "v3",
        "2/9"
    ]
}