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GET /api/patches/116559/?format=api
{ "id": 116559, "url": "http://patches.dpdk.org/api/patches/116559/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/eb1e2361d9d51e2d8eab328945d56130ee204916.1663767715.git.sthotton@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<eb1e2361d9d51e2d8eab328945d56130ee204916.1663767715.git.sthotton@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/eb1e2361d9d51e2d8eab328945d56130ee204916.1663767715.git.sthotton@marvell.com", "date": "2022-09-21T13:56:20", "name": "[v3,4/5] drivers: mark Marvell cnxk PMDs work with IOVA as VA", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d4baab1d9b3d26169befebbec051867d05aff3cb", "submitter": { "id": 2049, "url": "http://patches.dpdk.org/api/people/2049/?format=api", "name": "Shijith Thotton", "email": "sthotton@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/eb1e2361d9d51e2d8eab328945d56130ee204916.1663767715.git.sthotton@marvell.com/mbox/", "series": [ { "id": 24751, "url": "http://patches.dpdk.org/api/series/24751/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24751", "date": "2022-09-21T13:56:16", "name": "mbuf dynamic field expansion", "version": 3, "mbox": "http://patches.dpdk.org/series/24751/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/116559/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/116559/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 065FDA00C3;\n\tWed, 21 Sep 2022 15:57:15 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8565E427FF;\n\tWed, 21 Sep 2022 15:57:11 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 4CF434014F\n for <dev@dpdk.org>; Wed, 21 Sep 2022 15:57:09 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 28LBPtG8032713;\n Wed, 21 Sep 2022 06:57:05 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3jr1qmggj7-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 21 Sep 2022 06:57:04 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Wed, 21 Sep 2022 06:57:03 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 21 Sep 2022 06:57:03 -0700", "from localhost.localdomain (unknown [10.28.34.29])\n by maili.marvell.com (Postfix) with ESMTP id 7EF693F7041;\n Wed, 21 Sep 2022 06:56:56 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=lQ0lnX1BIeZbuMBNGz4lvsxXHkAErFrxRhXlmPX7PK4=;\n b=C/WULWPsXqvw5EdYpeJ9IXKI0XHPUXWxJi5SBJpG0OM/pWbYnmGfauy/v8/XHpi6Povs\n XQTSDNuTJC4b/H+0wQqThbWHe0GQ1o+HRyCIhLSdI76eK0fU4KiyoBi7aVtDtLDu8v/i\n i3zYlnOHXycgwl5jkOXLpR4DJdFwFyMM3KD++7QLD1YC+xoRIvYPjbgB+zGLkj1l5BS6\n rhaW7Z2a+seUjYjWinBzNp15xfSneNqSaDB+32W+yh8547flB8k08ZFDX4k+l7qJHQpc\n womSojX9HT8KUvR1QhomVoonDeeamKh3Cg4sQT7vZOurIrMJ35LMNulugEans1GrC/pJ yg==", "From": "Shijith Thotton <sthotton@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<pbhagavatula@marvell.com>, Shijith Thotton <sthotton@marvell.com>,\n <Honnappa.Nagarahalli@arm.com>, <bruce.richardson@intel.com>,\n <jerinj@marvell.com>, <mb@smartsharesystems.com>,\n <olivier.matz@6wind.com>, <stephen@networkplumber.org>,\n <thomas@monjalon.net>, <david.marchand@redhat.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>, \"Jan\n Viktorin\" <viktorin@rehivetech.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>, \"Sunil\n Kumar Kori\" <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com>, \"Ankur\n Dwivedi\" <adwivedi@marvell.com>, Anoob Joseph <anoobj@marvell.com>,\n \"Tejasree Kondoj\" <ktejasree@marvell.com>, Radha Mohan Chintakuntla\n <radhac@marvell.com>, Veerasenareddy Burru <vburru@marvell.com>, \"Ashwin\n Sekhar T K\" <asekhar@marvell.com>, Jakub Palider <jpalider@marvell.com>,\n Tomasz Duszynski <tduszynski@marvell.com>", "Subject": "[PATCH v3 4/5] drivers: mark Marvell cnxk PMDs work with IOVA as VA", "Date": "Wed, 21 Sep 2022 19:26:20 +0530", "Message-ID": "\n <eb1e2361d9d51e2d8eab328945d56130ee204916.1663767715.git.sthotton@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<cover.1663767715.git.sthotton@marvell.com>", "References": "<20220907134340.3629224-1-sthotton@marvell.com>\n <cover.1663767715.git.sthotton@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "ZjgDdCsZi5OGwiCY2ic6qgR-iQaJtwaV", "X-Proofpoint-ORIG-GUID": "ZjgDdCsZi5OGwiCY2ic6qgR-iQaJtwaV", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1\n definitions=2022-09-21_08,2022-09-20_02,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Enabled the flag pmd_iova_as_va in cnxk driver build files as they work\nwith IOVA as VA. Updated cn9k and cn10k soc build configurations to\nenable the IOVA as VA build by default.\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n config/arm/meson.build | 8 +++-\n drivers/common/cnxk/meson.build | 1 +\n drivers/crypto/cnxk/cn10k_ipsec_la_ops.h | 4 +-\n drivers/crypto/cnxk/cn9k_ipsec_la_ops.h | 2 +-\n drivers/crypto/cnxk/meson.build | 2 +\n drivers/dma/cnxk/meson.build | 1 +\n drivers/event/cnxk/meson.build | 1 +\n drivers/mempool/cnxk/meson.build | 1 +\n drivers/net/cnxk/cn10k_tx.h | 55 +++++++-----------------\n drivers/net/cnxk/cn9k_tx.h | 55 +++++++-----------------\n drivers/net/cnxk/cnxk_ethdev.h | 1 -\n drivers/net/cnxk/meson.build | 1 +\n drivers/raw/cnxk_bphy/meson.build | 1 +\n drivers/raw/cnxk_gpio/meson.build | 1 +\n 14 files changed, 50 insertions(+), 84 deletions(-)", "diff": "diff --git a/config/arm/meson.build b/config/arm/meson.build\nindex 9f1636e0d5..4e95e8b388 100644\n--- a/config/arm/meson.build\n+++ b/config/arm/meson.build\n@@ -294,7 +294,8 @@ soc_cn10k = {\n 'flags': [\n ['RTE_MAX_LCORE', 24],\n ['RTE_MAX_NUMA_NODES', 1],\n- ['RTE_MEMPOOL_ALIGN', 128]\n+ ['RTE_MEMPOOL_ALIGN', 128],\n+ ['RTE_IOVA_AS_VA', 1]\n ],\n 'part_number': '0xd49',\n 'extra_march_features': ['crypto'],\n@@ -370,7 +371,10 @@ soc_cn9k = {\n 'description': 'Marvell OCTEON 9',\n 'implementer': '0x43',\n 'part_number': '0xb2',\n- 'numa': false\n+ 'numa': false,\n+ 'flags': [\n+ ['RTE_IOVA_AS_VA', 1]\n+ ]\n }\n \n soc_stingray = {\ndiff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 6f808271d1..d019cfa8d1 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -86,3 +86,4 @@ sources += files('cnxk_telemetry_bphy.c',\n )\n \n deps += ['bus_pci', 'net', 'telemetry']\n+pmd_iova_as_va = true\ndiff --git a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h\nindex 66cfe6ca98..16db14344d 100644\n--- a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h\n+++ b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h\n@@ -85,7 +85,7 @@ process_outb_sa(struct roc_cpt_lf *lf, struct rte_crypto_op *cop,\n \n \t/* Prepare CPT instruction */\n \tinst->w4.u64 = inst_w4_u64 | rte_pktmbuf_pkt_len(m_src);\n-\tdptr = rte_pktmbuf_iova(m_src);\n+\tdptr = rte_pktmbuf_mtod(m_src, uint64_t);\n \tinst->dptr = dptr;\n \tinst->rptr = dptr;\n \n@@ -102,7 +102,7 @@ process_inb_sa(struct rte_crypto_op *cop, struct cn10k_ipsec_sa *sa,\n \n \t/* Prepare CPT instruction */\n \tinst->w4.u64 = sa->inst.w4 | rte_pktmbuf_pkt_len(m_src);\n-\tdptr = rte_pktmbuf_iova(m_src);\n+\tdptr = rte_pktmbuf_mtod(m_src, uint64_t);\n \tinst->dptr = dptr;\n \tinst->rptr = dptr;\n \ndiff --git a/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h b/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h\nindex e469596756..8b68e4c728 100644\n--- a/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h\n+++ b/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h\n@@ -99,7 +99,7 @@ process_inb_sa(struct rte_crypto_op *cop, struct cn9k_ipsec_sa *sa,\n \n \t/* Prepare CPT instruction */\n \tinst->w4.u64 = sa->inst.w4 | rte_pktmbuf_pkt_len(m_src);\n-\tinst->dptr = inst->rptr = rte_pktmbuf_iova(m_src);\n+\tinst->dptr = inst->rptr = rte_pktmbuf_mtod(m_src, uint64_t);\n \tinst->w7.u64 = sa->inst.w7;\n }\n #endif /* __CN9K_IPSEC_LA_OPS_H__ */\ndiff --git a/drivers/crypto/cnxk/meson.build b/drivers/crypto/cnxk/meson.build\nindex 23a1cc3aac..764e7bb99a 100644\n--- a/drivers/crypto/cnxk/meson.build\n+++ b/drivers/crypto/cnxk/meson.build\n@@ -31,3 +31,5 @@ if get_option('buildtype').contains('debug')\n else\n cflags += [ '-ULA_IPSEC_DEBUG' ]\n endif\n+\n+pmd_iova_as_va = true\ndiff --git a/drivers/dma/cnxk/meson.build b/drivers/dma/cnxk/meson.build\nindex d4be4ee860..ef0e3db109 100644\n--- a/drivers/dma/cnxk/meson.build\n+++ b/drivers/dma/cnxk/meson.build\n@@ -3,3 +3,4 @@\n \n deps += ['bus_pci', 'common_cnxk', 'dmadev']\n sources = files('cnxk_dmadev.c')\n+pmd_iova_as_va = true\ndiff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build\nindex b27bae7b12..650d0d4256 100644\n--- a/drivers/event/cnxk/meson.build\n+++ b/drivers/event/cnxk/meson.build\n@@ -479,3 +479,4 @@ foreach flag: extra_flags\n endforeach\n \n deps += ['bus_pci', 'common_cnxk', 'net_cnxk', 'crypto_cnxk']\n+pmd_iova_as_va = true\ndiff --git a/drivers/mempool/cnxk/meson.build b/drivers/mempool/cnxk/meson.build\nindex d5d1978569..a328176457 100644\n--- a/drivers/mempool/cnxk/meson.build\n+++ b/drivers/mempool/cnxk/meson.build\n@@ -17,3 +17,4 @@ sources = files(\n )\n \n deps += ['eal', 'mbuf', 'kvargs', 'bus_pci', 'common_cnxk', 'mempool']\n+pmd_iova_as_va = true\ndiff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h\nindex ea13866b20..2ef62da132 100644\n--- a/drivers/net/cnxk/cn10k_tx.h\n+++ b/drivers/net/cnxk/cn10k_tx.h\n@@ -1775,14 +1775,6 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,\n \t\tmbuf2 = (uint64_t *)tx_pkts[2];\n \t\tmbuf3 = (uint64_t *)tx_pkts[3];\n \n-\t\tmbuf0 = (uint64_t *)((uintptr_t)mbuf0 +\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf1 = (uint64_t *)((uintptr_t)mbuf1 +\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf2 = (uint64_t *)((uintptr_t)mbuf2 +\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf3 = (uint64_t *)((uintptr_t)mbuf3 +\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n \t\t/*\n \t\t * Get mbuf's, olflags, iova, pktlen, dataoff\n \t\t * dataoff_iovaX.D[0] = iova,\n@@ -1790,28 +1782,24 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,\n \t\t * len_olflagsX.D[0] = ol_flags,\n \t\t * len_olflagsX.D[1](63:32) = mbuf->pkt_len\n \t\t */\n-\t\tdataoff_iova0 = vld1q_u64(mbuf0);\n-\t\tlen_olflags0 = vld1q_u64(mbuf0 + 2);\n-\t\tdataoff_iova1 = vld1q_u64(mbuf1);\n-\t\tlen_olflags1 = vld1q_u64(mbuf1 + 2);\n-\t\tdataoff_iova2 = vld1q_u64(mbuf2);\n-\t\tlen_olflags2 = vld1q_u64(mbuf2 + 2);\n-\t\tdataoff_iova3 = vld1q_u64(mbuf3);\n-\t\tlen_olflags3 = vld1q_u64(mbuf3 + 2);\n+\t\tdataoff_iova0 =\n+\t\t\tvsetq_lane_u64(((struct rte_mbuf *)mbuf0)->data_off, vld1q_u64(mbuf0), 1);\n+\t\tlen_olflags0 = vld1q_u64(mbuf0 + 3);\n+\t\tdataoff_iova1 =\n+\t\t\tvsetq_lane_u64(((struct rte_mbuf *)mbuf0)->data_off, vld1q_u64(mbuf1), 1);\n+\t\tlen_olflags1 = vld1q_u64(mbuf1 + 3);\n+\t\tdataoff_iova2 =\n+\t\t\tvsetq_lane_u64(((struct rte_mbuf *)mbuf0)->data_off, vld1q_u64(mbuf2), 1);\n+\t\tlen_olflags2 = vld1q_u64(mbuf2 + 3);\n+\t\tdataoff_iova3 =\n+\t\t\tvsetq_lane_u64(((struct rte_mbuf *)mbuf0)->data_off, vld1q_u64(mbuf3), 1);\n+\t\tlen_olflags3 = vld1q_u64(mbuf3 + 3);\n \n \t\t/* Move mbufs to point pool */\n-\t\tmbuf0 = (uint64_t *)((uintptr_t)mbuf0 +\n-\t\t\t\t offsetof(struct rte_mbuf, pool) -\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf1 = (uint64_t *)((uintptr_t)mbuf1 +\n-\t\t\t\t offsetof(struct rte_mbuf, pool) -\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf2 = (uint64_t *)((uintptr_t)mbuf2 +\n-\t\t\t\t offsetof(struct rte_mbuf, pool) -\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf3 = (uint64_t *)((uintptr_t)mbuf3 +\n-\t\t\t\t offsetof(struct rte_mbuf, pool) -\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n+\t\tmbuf0 = (uint64_t *)((uintptr_t)mbuf0 + offsetof(struct rte_mbuf, pool));\n+\t\tmbuf1 = (uint64_t *)((uintptr_t)mbuf1 + offsetof(struct rte_mbuf, pool));\n+\t\tmbuf2 = (uint64_t *)((uintptr_t)mbuf2 + offsetof(struct rte_mbuf, pool));\n+\t\tmbuf3 = (uint64_t *)((uintptr_t)mbuf3 + offsetof(struct rte_mbuf, pool));\n \n \t\tif (flags & (NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |\n \t\t\t NIX_TX_OFFLOAD_L3_L4_CSUM_F)) {\n@@ -1861,17 +1849,6 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws,\n \t\txtmp128 = vzip2q_u64(len_olflags0, len_olflags1);\n \t\tytmp128 = vzip2q_u64(len_olflags2, len_olflags3);\n \n-\t\t/* Clear dataoff_iovaX.D[1] bits other than dataoff(15:0) */\n-\t\tconst uint64x2_t and_mask0 = {\n-\t\t\t0xFFFFFFFFFFFFFFFF,\n-\t\t\t0x000000000000FFFF,\n-\t\t};\n-\n-\t\tdataoff_iova0 = vandq_u64(dataoff_iova0, and_mask0);\n-\t\tdataoff_iova1 = vandq_u64(dataoff_iova1, and_mask0);\n-\t\tdataoff_iova2 = vandq_u64(dataoff_iova2, and_mask0);\n-\t\tdataoff_iova3 = vandq_u64(dataoff_iova3, and_mask0);\n-\n \t\t/*\n \t\t * Pick only 16 bits of pktlen preset at bits 63:32\n \t\t * and place them at bits 15:0.\ndiff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h\nindex 6ce81f5c96..f5d99ccb5a 100644\n--- a/drivers/net/cnxk/cn9k_tx.h\n+++ b/drivers/net/cnxk/cn9k_tx.h\n@@ -1005,14 +1005,6 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tmbuf2 = (uint64_t *)tx_pkts[2];\n \t\tmbuf3 = (uint64_t *)tx_pkts[3];\n \n-\t\tmbuf0 = (uint64_t *)((uintptr_t)mbuf0 +\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf1 = (uint64_t *)((uintptr_t)mbuf1 +\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf2 = (uint64_t *)((uintptr_t)mbuf2 +\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf3 = (uint64_t *)((uintptr_t)mbuf3 +\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n \t\t/*\n \t\t * Get mbuf's, olflags, iova, pktlen, dataoff\n \t\t * dataoff_iovaX.D[0] = iova,\n@@ -1020,28 +1012,24 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t * len_olflagsX.D[0] = ol_flags,\n \t\t * len_olflagsX.D[1](63:32) = mbuf->pkt_len\n \t\t */\n-\t\tdataoff_iova0 = vld1q_u64(mbuf0);\n-\t\tlen_olflags0 = vld1q_u64(mbuf0 + 2);\n-\t\tdataoff_iova1 = vld1q_u64(mbuf1);\n-\t\tlen_olflags1 = vld1q_u64(mbuf1 + 2);\n-\t\tdataoff_iova2 = vld1q_u64(mbuf2);\n-\t\tlen_olflags2 = vld1q_u64(mbuf2 + 2);\n-\t\tdataoff_iova3 = vld1q_u64(mbuf3);\n-\t\tlen_olflags3 = vld1q_u64(mbuf3 + 2);\n+\t\tdataoff_iova0 =\n+\t\t\tvsetq_lane_u64(((struct rte_mbuf *)mbuf0)->data_off, vld1q_u64(mbuf0), 1);\n+\t\tlen_olflags0 = vld1q_u64(mbuf0 + 3);\n+\t\tdataoff_iova1 =\n+\t\t\tvsetq_lane_u64(((struct rte_mbuf *)mbuf1)->data_off, vld1q_u64(mbuf1), 1);\n+\t\tlen_olflags1 = vld1q_u64(mbuf1 + 3);\n+\t\tdataoff_iova2 =\n+\t\t\tvsetq_lane_u64(((struct rte_mbuf *)mbuf2)->data_off, vld1q_u64(mbuf2), 1);\n+\t\tlen_olflags2 = vld1q_u64(mbuf2 + 3);\n+\t\tdataoff_iova3 =\n+\t\t\tvsetq_lane_u64(((struct rte_mbuf *)mbuf3)->data_off, vld1q_u64(mbuf3), 1);\n+\t\tlen_olflags3 = vld1q_u64(mbuf3 + 3);\n \n \t\t/* Move mbufs to point pool */\n-\t\tmbuf0 = (uint64_t *)((uintptr_t)mbuf0 +\n-\t\t\t\t offsetof(struct rte_mbuf, pool) -\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf1 = (uint64_t *)((uintptr_t)mbuf1 +\n-\t\t\t\t offsetof(struct rte_mbuf, pool) -\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf2 = (uint64_t *)((uintptr_t)mbuf2 +\n-\t\t\t\t offsetof(struct rte_mbuf, pool) -\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf3 = (uint64_t *)((uintptr_t)mbuf3 +\n-\t\t\t\t offsetof(struct rte_mbuf, pool) -\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n+\t\tmbuf0 = (uint64_t *)((uintptr_t)mbuf0 + offsetof(struct rte_mbuf, pool));\n+\t\tmbuf1 = (uint64_t *)((uintptr_t)mbuf1 + offsetof(struct rte_mbuf, pool));\n+\t\tmbuf2 = (uint64_t *)((uintptr_t)mbuf2 + offsetof(struct rte_mbuf, pool));\n+\t\tmbuf3 = (uint64_t *)((uintptr_t)mbuf3 + offsetof(struct rte_mbuf, pool));\n \n \t\tif (flags & (NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |\n \t\t\t NIX_TX_OFFLOAD_L3_L4_CSUM_F)) {\n@@ -1091,17 +1079,6 @@ cn9k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\txtmp128 = vzip2q_u64(len_olflags0, len_olflags1);\n \t\tytmp128 = vzip2q_u64(len_olflags2, len_olflags3);\n \n-\t\t/* Clear dataoff_iovaX.D[1] bits other than dataoff(15:0) */\n-\t\tconst uint64x2_t and_mask0 = {\n-\t\t\t0xFFFFFFFFFFFFFFFF,\n-\t\t\t0x000000000000FFFF,\n-\t\t};\n-\n-\t\tdataoff_iova0 = vandq_u64(dataoff_iova0, and_mask0);\n-\t\tdataoff_iova1 = vandq_u64(dataoff_iova1, and_mask0);\n-\t\tdataoff_iova2 = vandq_u64(dataoff_iova2, and_mask0);\n-\t\tdataoff_iova3 = vandq_u64(dataoff_iova3, and_mask0);\n-\n \t\t/*\n \t\t * Pick only 16 bits of pktlen preset at bits 63:32\n \t\t * and place them at bits 15:0.\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 4cb7c9e90c..abf1e4215f 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -690,7 +690,6 @@ cnxk_pktmbuf_detach(struct rte_mbuf *m)\n \n \tm->priv_size = priv_size;\n \tm->buf_addr = (char *)m + mbuf_size;\n-\tm->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;\n \tm->buf_len = (uint16_t)buf_len;\n \trte_pktmbuf_reset_headroom(m);\n \tm->data_len = 0;\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex f347e98fce..01489b3a36 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -194,3 +194,4 @@ foreach flag: extra_flags\n endforeach\n \n headers = files('rte_pmd_cnxk.h')\n+pmd_iova_as_va = true\ndiff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build\nindex 14147feaf4..781ed63e05 100644\n--- a/drivers/raw/cnxk_bphy/meson.build\n+++ b/drivers/raw/cnxk_bphy/meson.build\n@@ -10,3 +10,4 @@ sources = files(\n 'cnxk_bphy_irq.c',\n )\n headers = files('rte_pmd_bphy.h')\n+pmd_iova_as_va = true\ndiff --git a/drivers/raw/cnxk_gpio/meson.build b/drivers/raw/cnxk_gpio/meson.build\nindex a75a5b9084..f9aed173b6 100644\n--- a/drivers/raw/cnxk_gpio/meson.build\n+++ b/drivers/raw/cnxk_gpio/meson.build\n@@ -9,3 +9,4 @@ sources = files(\n 'cnxk_gpio_selftest.c',\n )\n headers = files('rte_pmd_cnxk_gpio.h')\n+pmd_iova_as_va = true\n", "prefixes": [ "v3", "4/5" ] }