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GET /api/patches/116432/?format=api
{ "id": 116432, "url": "http://patches.dpdk.org/api/patches/116432/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220919124117.1059642-2-skori@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220919124117.1059642-2-skori@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220919124117.1059642-2-skori@marvell.com", "date": "2022-09-19T12:41:16", "name": "[2/3] common/cnxk: add congestion management ROC APIs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7648b6364b193c4ff3f05010799c09ade64b2e2b", "submitter": { "id": 1318, "url": "http://patches.dpdk.org/api/people/1318/?format=api", "name": "Sunil Kumar Kori", "email": "skori@marvell.com" }, "delegate": { "id": 3961, "url": "http://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220919124117.1059642-2-skori@marvell.com/mbox/", "series": [ { "id": 24712, "url": "http://patches.dpdk.org/api/series/24712/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24712", "date": "2022-09-19T12:41:15", "name": "[1/3] app/testpmd: support congestion management CLIs", "version": 1, "mbox": "http://patches.dpdk.org/series/24712/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/116432/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/116432/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 074FAA00C3;\n\tMon, 19 Sep 2022 14:43:35 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DFC0B40E0F;\n\tMon, 19 Sep 2022 14:43:34 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 04D7340141\n for <dev@dpdk.org>; Mon, 19 Sep 2022 14:43:32 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 28J5EYue010907;\n Mon, 19 Sep 2022 05:41:26 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3jndrmp7d1-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 19 Sep 2022 05:41:26 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 19 Sep 2022 05:41:24 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 19 Sep 2022 05:41:24 -0700", "from localhost.localdomain (unknown [10.28.34.25])\n by maili.marvell.com (Postfix) with ESMTP id 85B6B3F7080;\n Mon, 19 Sep 2022 05:41:22 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=NRZ3kvPgg2BwFtszoI9GRK6p2QjlVj59/mUTV/N26Q4=;\n b=T4n6FmsXZFEbWGxaYJmXkOOqpE7wV06GEJE5uUt9TbRqMqPemdq/zB3xXCm5XbEEt/b1\n v4TIh+yPqssT9SjGl/8yMF/ITaG7jJGkcNXWGx4DqeE0BHj0C8jM/NS6CJpX/eT+QIfY\n CXZ4jd6z9FsVQFG/76QYjRd77eCPciXLAGRGADfzJfc4NHupM5D4cYP1hYHvRQ7MeS8h\n nPUefxnxmVSHKTRXBO/7gZKIrQSujjOcDYUQgvmESRWkXrVn6uaAT0g3ye96eT0hyVxv\n dvjqZzJK8R5tyOsaRZG82xCZWbUbPydB+zzbXkdghjXKl5dYT5Ak26Jf5/IGtS4jxtI4 GQ==", "From": "<skori@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 2/3] common/cnxk: add congestion management ROC APIs", "Date": "Mon, 19 Sep 2022 18:11:16 +0530", "Message-ID": "<20220919124117.1059642-2-skori@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220919124117.1059642-1-skori@marvell.com>", "References": "<20220919124117.1059642-1-skori@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "YAu-FoWpbU7nrnWVMwEWuk9u7PVxl9hf", "X-Proofpoint-ORIG-GUID": "YAu-FoWpbU7nrnWVMwEWuk9u7PVxl9hf", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1\n definitions=2022-09-19_05,2022-09-16_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nAdd congestion management RoC APIs.\n\nDepends-on: patch-24710 (\"ethdev: support congestion management\")\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 5 ++\n drivers/common/cnxk/roc_nix_queue.c | 106 ++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 1 +\n 3 files changed, 112 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 5c2a869eba..34cb2c717c 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -315,6 +315,10 @@ struct roc_nix_rq {\n \t/* Average SPB aura level drop threshold for RED */\n \tuint8_t spb_red_drop;\n \t/* Average SPB aura level pass threshold for RED */\n+\tuint8_t xqe_red_pass;\n+\t/* Average xqe level drop threshold for RED */\n+\tuint8_t xqe_red_drop;\n+\t/* Average xqe level pass threshold for RED */\n \tuint8_t spb_red_pass;\n \t/* LPB aura drop enable */\n \tbool lpb_drop_ena;\n@@ -869,6 +873,7 @@ int __roc_api roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq,\n \t\t\t bool ena);\n int __roc_api roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq,\n \t\t\t\tbool ena);\n+int __roc_api roc_nix_rq_cman_config(struct roc_nix *roc_nix, struct roc_nix_rq *rq);\n int __roc_api roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable);\n int __roc_api roc_nix_rq_is_sso_enable(struct roc_nix *roc_nix, uint32_t qid);\n int __roc_api roc_nix_rq_fini(struct roc_nix_rq *rq);\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 405d9a8274..368f1a52f7 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -235,6 +235,46 @@ nix_rq_aura_buf_type_update(struct roc_nix_rq *rq, bool set)\n \treturn 0;\n }\n \n+static int\n+nix_rq_cn9k_cman_cfg(struct dev *dev, struct roc_nix_rq *rq)\n+{\n+\tstruct mbox *mbox = dev->mbox;\n+\tstruct nix_aq_enq_req *aq;\n+\n+\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\tif (!aq)\n+\t\treturn -ENOSPC;\n+\n+\taq->qidx = rq->qid;\n+\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\tif (rq->red_pass && (rq->red_pass >= rq->red_drop)) {\n+\t\taq->rq.lpb_pool_pass = rq->red_pass;\n+\t\taq->rq.lpb_pool_drop = rq->red_drop;\n+\t\taq->rq_mask.lpb_pool_pass = ~(aq->rq_mask.lpb_pool_pass);\n+\t\taq->rq_mask.lpb_pool_drop = ~(aq->rq_mask.lpb_pool_drop);\n+\n+\t}\n+\n+\tif (rq->spb_red_pass && (rq->spb_red_pass >= rq->spb_red_drop)) {\n+\t\taq->rq.spb_pool_pass = rq->spb_red_pass;\n+\t\taq->rq.spb_pool_drop = rq->spb_red_drop;\n+\t\taq->rq_mask.spb_pool_pass = ~(aq->rq_mask.spb_pool_pass);\n+\t\taq->rq_mask.spb_pool_drop = ~(aq->rq_mask.spb_pool_drop);\n+\n+\t}\n+\n+\tif (rq->xqe_red_pass && (rq->xqe_red_pass >= rq->xqe_red_drop)) {\n+\t\taq->rq.xqe_pass = rq->xqe_red_pass;\n+\t\taq->rq.xqe_drop = rq->xqe_red_drop;\n+\t\taq->rq_mask.xqe_drop = ~(aq->rq_mask.xqe_drop);\n+\t\taq->rq_mask.xqe_pass = ~(aq->rq_mask.xqe_pass);\n+\t}\n+\n+\treturn mbox_process(mbox);\n+}\n+\n int\n nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,\n \t\tbool cfg, bool ena)\n@@ -529,6 +569,46 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n \treturn 0;\n }\n \n+static int\n+nix_rq_cman_cfg(struct dev *dev, struct roc_nix_rq *rq)\n+{\n+\tstruct nix_cn10k_aq_enq_req *aq;\n+\tstruct mbox *mbox = dev->mbox;\n+\n+\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\tif (!aq)\n+\t\treturn -ENOSPC;\n+\n+\taq->qidx = rq->qid;\n+\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\tif (rq->red_pass && (rq->red_pass >= rq->red_drop)) {\n+\t\taq->rq.lpb_pool_pass = rq->red_pass;\n+\t\taq->rq.lpb_pool_drop = rq->red_drop;\n+\t\taq->rq_mask.lpb_pool_pass = ~(aq->rq_mask.lpb_pool_pass);\n+\t\taq->rq_mask.lpb_pool_drop = ~(aq->rq_mask.lpb_pool_drop);\n+\n+\t}\n+\n+\tif (rq->spb_red_pass && (rq->spb_red_pass >= rq->spb_red_drop)) {\n+\t\taq->rq.spb_pool_pass = rq->spb_red_pass;\n+\t\taq->rq.spb_pool_drop = rq->spb_red_drop;\n+\t\taq->rq_mask.spb_pool_pass = ~(aq->rq_mask.spb_pool_pass);\n+\t\taq->rq_mask.spb_pool_drop = ~(aq->rq_mask.spb_pool_drop);\n+\n+\t}\n+\n+\tif (rq->xqe_red_pass && (rq->xqe_red_pass >= rq->xqe_red_drop)) {\n+\t\taq->rq.xqe_pass = rq->xqe_red_pass;\n+\t\taq->rq.xqe_drop = rq->xqe_red_drop;\n+\t\taq->rq_mask.xqe_drop = ~(aq->rq_mask.xqe_drop);\n+\t\taq->rq_mask.xqe_pass = ~(aq->rq_mask.xqe_pass);\n+\t}\n+\n+\treturn mbox_process(mbox);\n+}\n+\n int\n roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n {\n@@ -616,6 +696,32 @@ roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \treturn nix_tel_node_add_rq(rq);\n }\n \n+int\n+roc_nix_rq_cman_config(struct roc_nix *roc_nix, struct roc_nix_rq *rq)\n+{\n+\tbool is_cn9k = roc_model_is_cn9k();\n+\tstruct nix *nix;\n+\tstruct dev *dev;\n+\tint rc;\n+\n+\tif (roc_nix == NULL || rq == NULL)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tnix = roc_nix_to_nix_priv(roc_nix);\n+\n+\tif (rq->qid >= nix->nb_rx_queues)\n+\t\treturn NIX_ERR_QUEUE_INVALID_RANGE;\n+\n+\tdev = &nix->dev;\n+\n+\tif (is_cn9k)\n+\t\trc = nix_rq_cn9k_cman_cfg(dev, rq);\n+\telse\n+\t\trc = nix_rq_cman_cfg(dev, rq);\n+\n+\treturn rc;\n+}\n+\n int\n roc_nix_rq_fini(struct roc_nix_rq *rq)\n {\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 276fec3660..e935f17c28 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -228,6 +228,7 @@ INTERNAL {\n \troc_nix_reassembly_configure;\n \troc_nix_register_cq_irqs;\n \troc_nix_register_queue_irqs;\n+\troc_nix_rq_cman_config;\n \troc_nix_rq_dump;\n \troc_nix_rq_ena_dis;\n \troc_nix_rq_fini;\n", "prefixes": [ "2/3" ] }