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GET /api/patches/115062/?format=api
{ "id": 115062, "url": "http://patches.dpdk.org/api/patches/115062/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220815073206.2917968-35-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220815073206.2917968-35-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220815073206.2917968-35-qi.z.zhang@intel.com", "date": "2022-08-15T07:31:30", "name": "[v2,34/70] net/ice/base: fix null pointer dereference during", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6d168e2b23d63bc1b8a342bbd8859a7e00c7067a", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220815073206.2917968-35-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 24308, "url": "http://patches.dpdk.org/api/series/24308/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24308", "date": "2022-08-15T07:30:56", "name": "ice base code update", "version": 2, "mbox": "http://patches.dpdk.org/series/24308/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/115062/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/115062/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D751DA00C3;\n\tMon, 15 Aug 2022 01:25:29 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E98E942C96;\n\tMon, 15 Aug 2022 01:23:14 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id 5848342C91;\n Mon, 15 Aug 2022 01:23:13 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Aug 2022 16:23:12 -0700", "from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4])\n by orsmga008.jf.intel.com with ESMTP; 14 Aug 2022 16:23:10 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1660519393; x=1692055393;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=Gq8duh4RWWtOG5oLZDjXaAQ1jsY2TLLyDX8mntMFP1E=;\n b=VRQsGcciurj5ymrxNP8xufMKDKVXpzoFjEmnqWpDmEZZishG6A0zFi7Y\n ALAHd1rma7juJhk31j9w3dRGX8JJ2dBCkHI818tHGk0Fkaayg9YL/ZBGE\n dWVEzdDii858l4tHmGSa6exJbufavcJSb4fF3MZVC923ELsQihLhc/3d8\n rBDeCmJSn+rh35SijCoVdVxXiWUr1qf34NOdDGH+TNsL1VPd23ZzSCV67\n +7iMM1ryRUyM1w7BBlz8lzKiPxdSgDKSOcZSHL4ZlsWFhYEr3rP1Q6hGV\n UJW+fS2/7/AVNve2LCMPeKWDGMEUcKIFv5DSHs22yy+J4y6PtvOJAqPoj g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10439\"; a=\"291857974\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"291857974\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"635283183\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>, stable@dpdk.org,\n Roman Storozhenko <roman.storozhenko@intel.com>", "Subject": "[PATCH v2 34/70] net/ice/base: fix null pointer dereference during", "Date": "Mon, 15 Aug 2022 03:31:30 -0400", "Message-Id": "<20220815073206.2917968-35-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220815073206.2917968-1-qi.z.zhang@intel.com>", "References": "<20220815071306.2910599-1-qi.z.zhang@intel.com>\n <20220815073206.2917968-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Sometimes, during the shutdown process, an PCIe unrecoverable error\noccurs. This leads to the following NULL pointer dereference error\nwhile clearing hardware tables:\n\nThe patch fixes this bug by checking every table pointer against\nNULL before reference it, as some of them probably have been cleared\nin advance.\n\nFixes: 969890d505b1 (\"net/ice/base: enable clearing of HW tables\")\nCc: stable@dpdk.org\n\nSigned-off-by: Roman Storozhenko <roman.storozhenko@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_flex_pipe.c | 332 +++++++++++++++------------\n 1 file changed, 179 insertions(+), 153 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex aea0d97b9d..2d95ce4d74 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -2144,6 +2144,129 @@ void ice_init_flow_profs(struct ice_hw *hw, u8 blk_idx)\n \tINIT_LIST_HEAD(&hw->fl_profs[blk_idx]);\n }\n \n+/**\n+ * ice_init_hw_tbls - init hardware table memory\n+ * @hw: pointer to the hardware structure\n+ */\n+enum ice_status ice_init_hw_tbls(struct ice_hw *hw)\n+{\n+\tu8 i;\n+\n+\tice_init_lock(&hw->rss_locks);\n+\tINIT_LIST_HEAD(&hw->rss_list_head);\n+\tif (!hw->dcf_enabled)\n+\t\tice_init_all_prof_masks(hw);\n+\tfor (i = 0; i < ICE_BLK_COUNT; i++) {\n+\t\tstruct ice_prof_redir *prof_redir = &hw->blk[i].prof_redir;\n+\t\tstruct ice_prof_tcam *prof = &hw->blk[i].prof;\n+\t\tstruct ice_xlt1 *xlt1 = &hw->blk[i].xlt1;\n+\t\tstruct ice_xlt2 *xlt2 = &hw->blk[i].xlt2;\n+\t\tstruct ice_es *es = &hw->blk[i].es;\n+\t\tu16 j;\n+\n+\t\tif (hw->blk[i].is_list_init)\n+\t\t\tcontinue;\n+\n+\t\tice_init_flow_profs(hw, i);\n+\t\tice_init_lock(&es->prof_map_lock);\n+\t\tINIT_LIST_HEAD(&es->prof_map);\n+\t\thw->blk[i].is_list_init = true;\n+\n+\t\thw->blk[i].overwrite = blk_sizes[i].overwrite;\n+\t\tes->reverse = blk_sizes[i].reverse;\n+\n+\t\txlt1->sid = ice_blk_sids[i][ICE_SID_XLT1_OFF];\n+\t\txlt1->count = blk_sizes[i].xlt1;\n+\n+\t\txlt1->ptypes = (struct ice_ptg_ptype *)\n+\t\t\tice_calloc(hw, xlt1->count, sizeof(*xlt1->ptypes));\n+\n+\t\tif (!xlt1->ptypes)\n+\t\t\tgoto err;\n+\n+\t\txlt1->ptg_tbl = (struct ice_ptg_entry *)\n+\t\t\tice_calloc(hw, ICE_MAX_PTGS, sizeof(*xlt1->ptg_tbl));\n+\n+\t\tif (!xlt1->ptg_tbl)\n+\t\t\tgoto err;\n+\n+\t\txlt1->t = (u8 *)ice_calloc(hw, xlt1->count, sizeof(*xlt1->t));\n+\t\tif (!xlt1->t)\n+\t\t\tgoto err;\n+\n+\t\txlt2->sid = ice_blk_sids[i][ICE_SID_XLT2_OFF];\n+\t\txlt2->count = blk_sizes[i].xlt2;\n+\n+\t\txlt2->vsis = (struct ice_vsig_vsi *)\n+\t\t\tice_calloc(hw, xlt2->count, sizeof(*xlt2->vsis));\n+\n+\t\tif (!xlt2->vsis)\n+\t\t\tgoto err;\n+\n+\t\txlt2->vsig_tbl = (struct ice_vsig_entry *)\n+\t\t\tice_calloc(hw, xlt2->count, sizeof(*xlt2->vsig_tbl));\n+\t\tif (!xlt2->vsig_tbl)\n+\t\t\tgoto err;\n+\n+\t\tfor (j = 0; j < xlt2->count; j++)\n+\t\t\tINIT_LIST_HEAD(&xlt2->vsig_tbl[j].prop_lst);\n+\n+\t\txlt2->t = (u16 *)ice_calloc(hw, xlt2->count, sizeof(*xlt2->t));\n+\t\tif (!xlt2->t)\n+\t\t\tgoto err;\n+\n+\t\tprof->sid = ice_blk_sids[i][ICE_SID_PR_OFF];\n+\t\tprof->count = blk_sizes[i].prof_tcam;\n+\t\tprof->max_prof_id = blk_sizes[i].prof_id;\n+\t\tprof->cdid_bits = blk_sizes[i].prof_cdid_bits;\n+\t\tprof->t = (struct ice_prof_tcam_entry *)\n+\t\t\tice_calloc(hw, prof->count, sizeof(*prof->t));\n+\n+\t\tif (!prof->t)\n+\t\t\tgoto err;\n+\n+\t\tprof_redir->sid = ice_blk_sids[i][ICE_SID_PR_REDIR_OFF];\n+\t\tprof_redir->count = blk_sizes[i].prof_redir;\n+\t\tprof_redir->t = (u8 *)ice_calloc(hw, prof_redir->count,\n+\t\t\t\t\t\t sizeof(*prof_redir->t));\n+\n+\t\tif (!prof_redir->t)\n+\t\t\tgoto err;\n+\n+\t\tes->sid = ice_blk_sids[i][ICE_SID_ES_OFF];\n+\t\tes->count = blk_sizes[i].es;\n+\t\tes->fvw = blk_sizes[i].fvw;\n+\t\tes->t = (struct ice_fv_word *)\n+\t\t\tice_calloc(hw, (u32)(es->count * es->fvw),\n+\t\t\t\t sizeof(*es->t));\n+\t\tif (!es->t)\n+\t\t\tgoto err;\n+\n+\t\tes->ref_count = (u16 *)\n+\t\t\tice_calloc(hw, es->count, sizeof(*es->ref_count));\n+\n+\t\tif (!es->ref_count)\n+\t\t\tgoto err;\n+\n+\t\tes->written = (u8 *)\n+\t\t\tice_calloc(hw, es->count, sizeof(*es->written));\n+\n+\t\tif (!es->written)\n+\t\t\tgoto err;\n+\n+\t\tes->mask_ena = (u32 *)\n+\t\t\tice_calloc(hw, es->count, sizeof(*es->mask_ena));\n+\n+\t\tif (!es->mask_ena)\n+\t\t\tgoto err;\n+\t}\n+\treturn ICE_SUCCESS;\n+\n+err:\n+\tice_free_hw_tbls(hw);\n+\treturn ICE_ERR_NO_MEMORY;\n+}\n+\n /**\n * ice_fill_blk_tbls - Read package context for tables\n * @hw: pointer to the hardware structure\n@@ -2308,162 +2431,65 @@ void ice_clear_hw_tbls(struct ice_hw *hw)\n \n \t\tice_free_vsig_tbl(hw, (enum ice_block)i);\n \n-\t\tice_memset(xlt1->ptypes, 0, xlt1->count * sizeof(*xlt1->ptypes),\n-\t\t\t ICE_NONDMA_MEM);\n-\t\tice_memset(xlt1->ptg_tbl, 0,\n-\t\t\t ICE_MAX_PTGS * sizeof(*xlt1->ptg_tbl),\n-\t\t\t ICE_NONDMA_MEM);\n-\t\tice_memset(xlt1->t, 0, xlt1->count * sizeof(*xlt1->t),\n-\t\t\t ICE_NONDMA_MEM);\n-\n-\t\tice_memset(xlt2->vsis, 0, xlt2->count * sizeof(*xlt2->vsis),\n-\t\t\t ICE_NONDMA_MEM);\n-\t\tice_memset(xlt2->vsig_tbl, 0,\n-\t\t\t xlt2->count * sizeof(*xlt2->vsig_tbl),\n-\t\t\t ICE_NONDMA_MEM);\n-\t\tice_memset(xlt2->t, 0, xlt2->count * sizeof(*xlt2->t),\n-\t\t\t ICE_NONDMA_MEM);\n-\n-\t\tice_memset(prof->t, 0, prof->count * sizeof(*prof->t),\n-\t\t\t ICE_NONDMA_MEM);\n-\t\tice_memset(prof_redir->t, 0,\n-\t\t\t prof_redir->count * sizeof(*prof_redir->t),\n-\t\t\t ICE_NONDMA_MEM);\n-\n-\t\tice_memset(es->t, 0, es->count * sizeof(*es->t) * es->fvw,\n-\t\t\t ICE_NONDMA_MEM);\n-\t\tice_memset(es->ref_count, 0, es->count * sizeof(*es->ref_count),\n-\t\t\t ICE_NONDMA_MEM);\n-\t\tice_memset(es->written, 0, es->count * sizeof(*es->written),\n-\t\t\t ICE_NONDMA_MEM);\n-\t\tice_memset(es->mask_ena, 0, es->count * sizeof(*es->mask_ena),\n-\t\t\t ICE_NONDMA_MEM);\n+\t\tif (xlt1->ptypes)\n+\t\t\tice_memset(xlt1->ptypes, 0,\n+\t\t\t\t xlt1->count * sizeof(*xlt1->ptypes),\n+\t\t\t\t ICE_NONDMA_MEM);\n+\n+\t\tif (xlt1->ptg_tbl)\n+\t\t\tice_memset(xlt1->ptg_tbl, 0,\n+\t\t\t\t ICE_MAX_PTGS * sizeof(*xlt1->ptg_tbl),\n+\t\t\t\t ICE_NONDMA_MEM);\n+\n+\t\tif (xlt1->t)\n+\t\t\tice_memset(xlt1->t, 0, xlt1->count * sizeof(*xlt1->t),\n+\t\t\t\t ICE_NONDMA_MEM);\n+\n+\t\tif (xlt2->vsis)\n+\t\t\tice_memset(xlt2->vsis, 0,\n+\t\t\t\t xlt2->count * sizeof(*xlt2->vsis),\n+\t\t\t\t ICE_NONDMA_MEM);\n+\n+\t\tif (xlt2->vsig_tbl)\n+\t\t\tice_memset(xlt2->vsig_tbl, 0,\n+\t\t\t\t xlt2->count * sizeof(*xlt2->vsig_tbl),\n+\t\t\t\t ICE_NONDMA_MEM);\n+\n+\t\tif (xlt2->t)\n+\t\t\tice_memset(xlt2->t, 0, xlt2->count * sizeof(*xlt2->t),\n+\t\t\t\t ICE_NONDMA_MEM);\n+\n+\t\tif (prof->t)\n+\t\t\tice_memset(prof->t, 0, prof->count * sizeof(*prof->t),\n+\t\t\t\t ICE_NONDMA_MEM);\n+\n+\t\tif (prof_redir->t)\n+\t\t\tice_memset(prof_redir->t, 0,\n+\t\t\t\t prof_redir->count * sizeof(*prof_redir->t),\n+\t\t\t\t ICE_NONDMA_MEM);\n+\n+\t\tif (es->t)\n+\t\t\tice_memset(es->t, 0,\n+\t\t\t\t es->count * sizeof(*es->t) * es->fvw,\n+\t\t\t\t ICE_NONDMA_MEM);\n+\n+\t\tif (es->ref_count)\n+\t\t\tice_memset(es->ref_count, 0,\n+\t\t\t\t es->count * sizeof(*es->ref_count),\n+\t\t\t\t ICE_NONDMA_MEM);\n+\n+\t\tif (es->written)\n+\t\t\tice_memset(es->written, 0,\n+\t\t\t\t es->count * sizeof(*es->written),\n+\t\t\t\t ICE_NONDMA_MEM);\n+\n+\t\tif (es->mask_ena)\n+\t\t\tice_memset(es->mask_ena, 0,\n+\t\t\t\t es->count * sizeof(*es->mask_ena),\n+\t\t\t\t ICE_NONDMA_MEM);\n \t}\n }\n \n-/**\n- * ice_init_hw_tbls - init hardware table memory\n- * @hw: pointer to the hardware structure\n- */\n-enum ice_status ice_init_hw_tbls(struct ice_hw *hw)\n-{\n-\tu8 i;\n-\n-\tice_init_lock(&hw->rss_locks);\n-\tINIT_LIST_HEAD(&hw->rss_list_head);\n-\tif (!hw->dcf_enabled)\n-\t\tice_init_all_prof_masks(hw);\n-\tfor (i = 0; i < ICE_BLK_COUNT; i++) {\n-\t\tstruct ice_prof_redir *prof_redir = &hw->blk[i].prof_redir;\n-\t\tstruct ice_prof_tcam *prof = &hw->blk[i].prof;\n-\t\tstruct ice_xlt1 *xlt1 = &hw->blk[i].xlt1;\n-\t\tstruct ice_xlt2 *xlt2 = &hw->blk[i].xlt2;\n-\t\tstruct ice_es *es = &hw->blk[i].es;\n-\t\tu16 j;\n-\n-\t\tif (hw->blk[i].is_list_init)\n-\t\t\tcontinue;\n-\n-\t\tice_init_flow_profs(hw, i);\n-\t\tice_init_lock(&es->prof_map_lock);\n-\t\tINIT_LIST_HEAD(&es->prof_map);\n-\t\thw->blk[i].is_list_init = true;\n-\n-\t\thw->blk[i].overwrite = blk_sizes[i].overwrite;\n-\t\tes->reverse = blk_sizes[i].reverse;\n-\n-\t\txlt1->sid = ice_blk_sids[i][ICE_SID_XLT1_OFF];\n-\t\txlt1->count = blk_sizes[i].xlt1;\n-\n-\t\txlt1->ptypes = (struct ice_ptg_ptype *)\n-\t\t\tice_calloc(hw, xlt1->count, sizeof(*xlt1->ptypes));\n-\n-\t\tif (!xlt1->ptypes)\n-\t\t\tgoto err;\n-\n-\t\txlt1->ptg_tbl = (struct ice_ptg_entry *)\n-\t\t\tice_calloc(hw, ICE_MAX_PTGS, sizeof(*xlt1->ptg_tbl));\n-\n-\t\tif (!xlt1->ptg_tbl)\n-\t\t\tgoto err;\n-\n-\t\txlt1->t = (u8 *)ice_calloc(hw, xlt1->count, sizeof(*xlt1->t));\n-\t\tif (!xlt1->t)\n-\t\t\tgoto err;\n-\n-\t\txlt2->sid = ice_blk_sids[i][ICE_SID_XLT2_OFF];\n-\t\txlt2->count = blk_sizes[i].xlt2;\n-\n-\t\txlt2->vsis = (struct ice_vsig_vsi *)\n-\t\t\tice_calloc(hw, xlt2->count, sizeof(*xlt2->vsis));\n-\n-\t\tif (!xlt2->vsis)\n-\t\t\tgoto err;\n-\n-\t\txlt2->vsig_tbl = (struct ice_vsig_entry *)\n-\t\t\tice_calloc(hw, xlt2->count, sizeof(*xlt2->vsig_tbl));\n-\t\tif (!xlt2->vsig_tbl)\n-\t\t\tgoto err;\n-\n-\t\tfor (j = 0; j < xlt2->count; j++)\n-\t\t\tINIT_LIST_HEAD(&xlt2->vsig_tbl[j].prop_lst);\n-\n-\t\txlt2->t = (u16 *)ice_calloc(hw, xlt2->count, sizeof(*xlt2->t));\n-\t\tif (!xlt2->t)\n-\t\t\tgoto err;\n-\n-\t\tprof->sid = ice_blk_sids[i][ICE_SID_PR_OFF];\n-\t\tprof->count = blk_sizes[i].prof_tcam;\n-\t\tprof->max_prof_id = blk_sizes[i].prof_id;\n-\t\tprof->cdid_bits = blk_sizes[i].prof_cdid_bits;\n-\t\tprof->t = (struct ice_prof_tcam_entry *)\n-\t\t\tice_calloc(hw, prof->count, sizeof(*prof->t));\n-\n-\t\tif (!prof->t)\n-\t\t\tgoto err;\n-\n-\t\tprof_redir->sid = ice_blk_sids[i][ICE_SID_PR_REDIR_OFF];\n-\t\tprof_redir->count = blk_sizes[i].prof_redir;\n-\t\tprof_redir->t = (u8 *)ice_calloc(hw, prof_redir->count,\n-\t\t\t\t\t\t sizeof(*prof_redir->t));\n-\n-\t\tif (!prof_redir->t)\n-\t\t\tgoto err;\n-\n-\t\tes->sid = ice_blk_sids[i][ICE_SID_ES_OFF];\n-\t\tes->count = blk_sizes[i].es;\n-\t\tes->fvw = blk_sizes[i].fvw;\n-\t\tes->t = (struct ice_fv_word *)\n-\t\t\tice_calloc(hw, (u32)(es->count * es->fvw),\n-\t\t\t\t sizeof(*es->t));\n-\t\tif (!es->t)\n-\t\t\tgoto err;\n-\n-\t\tes->ref_count = (u16 *)\n-\t\t\tice_calloc(hw, es->count, sizeof(*es->ref_count));\n-\n-\t\tif (!es->ref_count)\n-\t\t\tgoto err;\n-\n-\t\tes->written = (u8 *)\n-\t\t\tice_calloc(hw, es->count, sizeof(*es->written));\n-\n-\t\tif (!es->written)\n-\t\t\tgoto err;\n-\n-\t\tes->mask_ena = (u32 *)\n-\t\t\tice_calloc(hw, es->count, sizeof(*es->mask_ena));\n-\n-\t\tif (!es->mask_ena)\n-\t\t\tgoto err;\n-\t}\n-\treturn ICE_SUCCESS;\n-\n-err:\n-\tice_free_hw_tbls(hw);\n-\treturn ICE_ERR_NO_MEMORY;\n-}\n-\n /**\n * ice_prof_gen_key - generate profile ID key\n * @hw: pointer to the HW struct\n", "prefixes": [ "v2", "34/70" ] }