Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/115042/?format=api
{ "id": 115042, "url": "http://patches.dpdk.org/api/patches/115042/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220815073206.2917968-15-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220815073206.2917968-15-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220815073206.2917968-15-qi.z.zhang@intel.com", "date": "2022-08-15T07:31:10", "name": "[v2,14/70] net/ice/base: add 56G PHY register definitions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "9d73047b543378af1486812c6c990a574fa8d820", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220815073206.2917968-15-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 24308, "url": "http://patches.dpdk.org/api/series/24308/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24308", "date": "2022-08-15T07:30:56", "name": "ice base code update", "version": 2, "mbox": "http://patches.dpdk.org/series/24308/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/115042/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/115042/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 49C71A00C3;\n\tMon, 15 Aug 2022 01:23:38 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 93EC442BEA;\n\tMon, 15 Aug 2022 01:22:39 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id 19DAD42B8B\n for <dev@dpdk.org>; Mon, 15 Aug 2022 01:22:37 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Aug 2022 16:22:37 -0700", "from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4])\n by orsmga008.jf.intel.com with ESMTP; 14 Aug 2022 16:22:35 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1660519358; x=1692055358;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=+XtH/byjHTEF9mE0aq56QVmKojzZ8NOBMXPtQFGiHc4=;\n b=nVpVRdzeOTtKFTk1CHnJ+olnoE1L2rizjCEd8Vp32BeQPrVVVt/YGBBL\n leYuVGluM6ZXGT/Hg/VAtVWQ/NuTTFR0c+jEtfhUZBkaOG81j6XwsX3xN\n lXLxXYriGO5R8LQKBiXMdp0E6AKy47QmMUul6XHG1sBQK1NuvsRJj0lo6\n Xyycg1161ZRHZm3vIqXsEipfZFaUS9GhPEZoEZWwRGp4nmcEarAiUtjGM\n d9bk4SwTCUodRiUQFfOnBV75adsUgTlySwldFnYTtNqoj06Rxwl1044dx\n /kBKD00odhfqCoVpl6+/E6+R6UG8KL+TwIZS2050/gGKrVeM78XNHvfZf w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10439\"; a=\"291857935\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"291857935\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"635283055\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Sergey Temerkhanov <sergey.temerkhanov@intel.com>", "Subject": "[PATCH v2 14/70] net/ice/base: add 56G PHY register definitions", "Date": "Mon, 15 Aug 2022 03:31:10 -0400", "Message-Id": "<20220815073206.2917968-15-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220815073206.2917968-1-qi.z.zhang@intel.com>", "References": "<20220815071306.2910599-1-qi.z.zhang@intel.com>\n <20220815073206.2917968-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add 56G PHY register address definitions to facilitate 56G PHY\nsupport.\n\nSigned-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.h | 75 +++++++++++++++++++++++++++++++\n 1 file changed, 75 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h\nindex 9cc3436aa8..ecb79eaea9 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.h\n+++ b/drivers/net/ice/base/ice_ptp_hw.h\n@@ -482,5 +482,80 @@ bool ice_is_pca9575_present(struct ice_hw *hw);\n #define ICE_E810T_SMA_MIN_BIT\t3\n #define ICE_E810T_SMA_MAX_BIT\t7\n #define ICE_E810T_P1_OFFSET\t8\n+/* 56G PHY quad register base addresses */\n+#define ICE_PHY0_BASE\t\t\t0x092000\n+#define ICE_PHY1_BASE\t\t\t0x126000\n+#define ICE_PHY2_BASE\t\t\t0x1BA000\n+#define ICE_PHY3_BASE\t\t\t0x24E000\n+#define ICE_PHY4_BASE\t\t\t0x2E2000\n+\n+/* Timestamp memory */\n+#define PHY_PTP_LANE_ADDR_STEP\t\t0x98\n+\n+#define PHY_PTP_MEM_START\t\t0x1000\n+#define PHY_PTP_MEM_LANE_STEP\t\t0x04A0\n+#define PHY_PTP_MEM_LOCATIONS\t\t0x40\n+\n+/* Number of PHY ports */\n+#define ICE_NUM_PHY_PORTS\t\t5\n+/* Timestamp PHY incval registers */\n+#define PHY_REG_TIMETUS_L\t\t0x8\n+#define PHY_REG_TIMETUS_U\t\t0xC\n+\n+/* Timestamp init registers */\n+#define PHY_REG_RX_TIMER_INC_PRE_L\t0x64\n+#define PHY_REG_RX_TIMER_INC_PRE_U\t0x68\n+\n+#define PHY_REG_TX_TIMER_INC_PRE_L\t0x44\n+#define PHY_REG_TX_TIMER_INC_PRE_U\t0x48\n+\n+/* Timestamp match and adjust target registers */\n+#define PHY_REG_RX_TIMER_CNT_ADJ_L\t0x6C\n+#define PHY_REG_RX_TIMER_CNT_ADJ_U\t0x70\n+\n+#define PHY_REG_TX_TIMER_CNT_ADJ_L\t0x4C\n+#define PHY_REG_TX_TIMER_CNT_ADJ_U\t0x50\n+\n+/* Timestamp command registers */\n+#define PHY_REG_TX_TMR_CMD\t\t0x40\n+#define PHY_REG_RX_TMR_CMD\t\t0x60\n+\n+/* Phy offset ready registers */\n+#define PHY_REG_TX_OFFSET_READY\t\t0x54\n+#define PHY_REG_RX_OFFSET_READY\t\t0x74\n+/* Phy total offset registers */\n+#define PHY_REG_TOTAL_TX_OFFSET_L\t0x38\n+#define PHY_REG_TOTAL_TX_OFFSET_U\t0x3C\n+\n+#define PHY_REG_TOTAL_RX_OFFSET_L\t0x58\n+#define PHY_REG_TOTAL_RX_OFFSET_U\t0x5C\n+\n+/* Timestamp capture registers */\n+#define PHY_REG_TX_CAPTURE_L\t\t0x78\n+#define PHY_REG_TX_CAPTURE_U\t\t0x7C\n+\n+#define PHY_REG_RX_CAPTURE_L\t\t0x8C\n+#define PHY_REG_RX_CAPTURE_U\t\t0x90\n+\n+/* Memory status registers */\n+#define PHY_REG_TX_MEMORY_STATUS_L\t0x80\n+#define PHY_REG_TX_MEMORY_STATUS_U\t0x84\n+\n+/* Interrupt config register */\n+#define PHY_REG_TS_INT_CONFIG\t\t0x88\n+\n+#define PHY_PTP_INT_STATUS\t\t0x7FD140\n+\n+#define PHY_TS_INT_CONFIG_THRESHOLD_S\t0\n+#define PHY_TS_INT_CONFIG_THRESHOLD_M\tMAKEMASK(0x3F, 0)\n+#define PHY_TS_INT_CONFIG_ENA_S\t\t6\n+#define PHY_TS_INT_CONFIG_ENA_M\t\tBIT(6)\n+\n+/* Macros to derive offsets for TimeStampLow and TimeStampHigh */\n+#define PHY_TSTAMP_L(x) (((x) * 8) + 0)\n+#define PHY_TSTAMP_U(x) (((x) * 8) + 4)\n+\n+#define PHY_REG_REVISION\t\t0x85000\n+#define PHY_REVISION_ETH56G\t\t0x10200\n \n #endif /* _ICE_PTP_HW_H_ */\n", "prefixes": [ "v2", "14/70" ] }