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GET /api/patches/114995/?format=api
{ "id": 114995, "url": "http://patches.dpdk.org/api/patches/114995/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220815071306.2910599-39-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220815071306.2910599-39-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220815071306.2910599-39-qi.z.zhang@intel.com", "date": "2022-08-15T07:12:34", "name": "[38/70] net/ice/base: adjust the VSI/Aggregator layers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "88b85c231002aa4cc24334cf217d9482aa7680f9", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220815071306.2910599-39-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 24307, "url": "http://patches.dpdk.org/api/series/24307/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24307", "date": "2022-08-15T07:11:56", "name": "ice base code update", "version": 1, "mbox": "http://patches.dpdk.org/series/24307/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/114995/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/114995/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 340E1A00C4;\n\tMon, 15 Aug 2022 01:07:03 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 92A0F42C62;\n\tMon, 15 Aug 2022 01:04:13 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 5FB3242C29\n for <dev@dpdk.org>; Mon, 15 Aug 2022 01:04:11 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Aug 2022 16:04:11 -0700", "from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4])\n by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:04:09 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1660518251; x=1692054251;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=yCMLk9ixggGIqTdqjqwMOJLEjliWxZ7CUwWB2XuLdLI=;\n b=n176pKy4be/ro3nYXyt2ug9J20Ss/Cpahj4sE2DLKNQI4tA2RJ3xmFbE\n lie6csvseiCaMSGB5pcM2shWC+zxchu4qJqRupSWuXUf6oAg87cpzJ7l0\n JYtgXWpb6W92CMQ2+7du54E/+gkNj9Efabp4FMhGiZEj1p6QF1CRFZESU\n zk8lyzKsHijAwNxfzSzjRa+pcCjWwE2JGSEO1H2NcHKnP0s9YSheQ09SF\n HGEHvppIk7Dizkk12hgUgIc33DEK7WfJnpdsXulwxSY2BRQY3aA8rozuI\n AkrqQy4R2FX9DFwEJFtapEYXZ//2RI+043YQzjx7hPwPhqw8B1JR3mG3o w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10439\"; a=\"289427616\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"289427616\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"934296760\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Victor Raj <victor.raj@intel.com>", "Subject": "[PATCH 38/70] net/ice/base: adjust the VSI/Aggregator layers", "Date": "Mon, 15 Aug 2022 03:12:34 -0400", "Message-Id": "<20220815071306.2910599-39-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220815071306.2910599-1-qi.z.zhang@intel.com>", "References": "<20220815071306.2910599-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adjust the VSI/Aggregator layers based on the number of logical\nlayers supported by the FW. Currently the VSI and aggregator layers are\nfixed based on the 9 layer scheduler tree layout. Due to performance\nreasons the number of layers of the scheduler tree is changing from\n9 to 5. It requires a readjument of these VSI/Aggregator layer\nvalues.\n\nSigned-off-by: Victor Raj <victor.raj@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_sched.c | 34 ++++++++++++++++----------------\n drivers/net/ice/base/ice_sched.h | 3 +++\n 2 files changed, 20 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c\nindex 6f938d71a1..4d31e96fd0 100644\n--- a/drivers/net/ice/base/ice_sched.c\n+++ b/drivers/net/ice/base/ice_sched.c\n@@ -1130,12 +1130,11 @@ static u8 ice_sched_get_vsi_layer(struct ice_hw *hw)\n \t * 5 or less sw_entry_point_layer\n \t */\n \t/* calculate the VSI layer based on number of layers. */\n-\tif (hw->num_tx_sched_layers > ICE_VSI_LAYER_OFFSET + 1) {\n-\t\tu8 layer = hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET;\n-\n-\t\tif (layer > hw->sw_entry_point_layer)\n-\t\t\treturn layer;\n-\t}\n+\tif (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS)\n+\t\treturn hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET;\n+\telse if (hw->num_tx_sched_layers == ICE_SCHED_5_LAYERS)\n+\t\t/* qgroup and VSI layers are same */\n+\t\treturn hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET;\n \treturn hw->sw_entry_point_layer;\n }\n \n@@ -1152,12 +1151,8 @@ static u8 ice_sched_get_agg_layer(struct ice_hw *hw)\n \t * 7 or less sw_entry_point_layer\n \t */\n \t/* calculate the aggregator layer based on number of layers. */\n-\tif (hw->num_tx_sched_layers > ICE_AGG_LAYER_OFFSET + 1) {\n-\t\tu8 layer = hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET;\n-\n-\t\tif (layer > hw->sw_entry_point_layer)\n-\t\t\treturn layer;\n-\t}\n+\tif (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS)\n+\t\treturn hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET;\n \treturn hw->sw_entry_point_layer;\n }\n \n@@ -1542,10 +1537,11 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n {\n \tstruct ice_sched_node *vsi_node, *qgrp_node;\n \tstruct ice_vsi_ctx *vsi_ctx;\n+\tu8 qgrp_layer, vsi_layer;\n \tu16 max_children;\n-\tu8 qgrp_layer;\n \n \tqgrp_layer = ice_sched_get_qgrp_layer(pi->hw);\n+\tvsi_layer = ice_sched_get_vsi_layer(pi->hw);\n \tmax_children = pi->hw->max_children[qgrp_layer];\n \n \tvsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);\n@@ -1556,6 +1552,12 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n \tif (!vsi_node)\n \t\treturn NULL;\n \n+\t/* If the queue group and vsi layer are same then queues\n+\t * are all attached directly to VSI\n+\t */\n+\tif (qgrp_layer == vsi_layer)\n+\t\treturn vsi_node;\n+\n \t/* get the first queue group node from VSI sub-tree */\n \tqgrp_node = ice_sched_get_first_node(pi, vsi_node, qgrp_layer);\n \twhile (qgrp_node) {\n@@ -4060,7 +4062,7 @@ ice_sched_add_rl_profile(struct ice_hw *hw, enum ice_rl_type rl_type,\n \tenum ice_status status;\n \tu8 profile_type;\n \n-\tif (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)\n+\tif (!hw || layer_num >= hw->num_tx_sched_layers)\n \t\treturn NULL;\n \tswitch (rl_type) {\n \tcase ICE_MIN_BW:\n@@ -4076,8 +4078,6 @@ ice_sched_add_rl_profile(struct ice_hw *hw, enum ice_rl_type rl_type,\n \t\treturn NULL;\n \t}\n \n-\tif (!hw)\n-\t\treturn NULL;\n \tLIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num],\n \t\t\t ice_aqc_rl_profile_info, list_entry)\n \t\tif ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) ==\n@@ -4279,7 +4279,7 @@ ice_sched_rm_rl_profile(struct ice_hw *hw, u8 layer_num, u8 profile_type,\n \tstruct ice_aqc_rl_profile_info *rl_prof_elem;\n \tenum ice_status status = ICE_SUCCESS;\n \n-\tif (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)\n+\tif (!hw || layer_num >= hw->num_tx_sched_layers)\n \t\treturn ICE_ERR_PARAM;\n \t/* Check the existing list for RL profile */\n \tLIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num],\ndiff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h\nindex 6b12a0688a..53a68dbe51 100644\n--- a/drivers/net/ice/base/ice_sched.h\n+++ b/drivers/net/ice/base/ice_sched.h\n@@ -7,6 +7,9 @@\n \n #include \"ice_common.h\"\n \n+#define ICE_SCHED_5_LAYERS\t5\n+#define ICE_SCHED_9_LAYERS\t9\n+\n #define ICE_QGRP_LAYER_OFFSET\t2\n #define ICE_VSI_LAYER_OFFSET\t4\n #define ICE_AGG_LAYER_OFFSET\t6\n", "prefixes": [ "38/70" ] }