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GET /api/patches/114783/?format=api
{ "id": 114783, "url": "http://patches.dpdk.org/api/patches/114783/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220809184908.24030-23-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220809184908.24030-23-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220809184908.24030-23-ndabilpuram@marvell.com", "date": "2022-08-09T18:49:07", "name": "[23/23] common/cnxk: support Tx compl event via RQ to CQ mapping", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "5a52adc7f896d7c9e6a4f15c9fc0c1958aec44db", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220809184908.24030-23-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 24239, "url": "http://patches.dpdk.org/api/series/24239/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24239", "date": "2022-08-09T18:48:45", "name": "[01/23] common/cnxk: fix part value for cn10k", "version": 1, "mbox": "http://patches.dpdk.org/series/24239/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/114783/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/114783/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E964DA04FD;\n\tTue, 9 Aug 2022 20:51:40 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3BD6242C5B;\n\tTue, 9 Aug 2022 20:50:54 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 0EF4E42C42\n for <dev@dpdk.org>; Tue, 9 Aug 2022 20:50:52 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 279DD0Cu015646\n for <dev@dpdk.org>; Tue, 9 Aug 2022 11:50:52 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3huds2ukxt-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 09 Aug 2022 11:50:52 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 9 Aug 2022 11:50:50 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 9 Aug 2022 11:50:50 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 6559E3F7085;\n Tue, 9 Aug 2022 11:50:48 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=vwQHi4xxXzCRnDzDQpQVPnFV7f8Fwvg56pQVwc8Xk5Q=;\n b=j9WA4LF41zC4+92Tm5TlmvqcLj6PBqwd4RM1LKMNMr4Ue6xjyoo13o35F8bzCaMLnrRM\n KFIuIkKVVSWVJFAoDgtIqs+pXHnQ56Z9HEwDVsDoP6cXy3CCjGiYhpv5Qa7jMYMx5DBx\n BEyX5s39y/jT2F8KVFzW1pBiJCCkZyX8XhgQ3QRqHN9xB+AN4CRZCxWCp20niHTXn7sZ\n N8UMkgtty3KF0VIzS2XFe6WMge9Q9Lyr8k5uIAyJhDc++ZbBtl3lNQvPkpaWUb1wvtLO\n ry05jwXNCULUBoAHQnr0XPgTJVe272WGXgvFJpOG8AW/SVXVjMJX3EERYPSyiuOG3LVA ZQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>, Kommula Shiva Shankar\n <kshankar@marvell.com>", "Subject": "[PATCH 23/23] common/cnxk: support Tx compl event via RQ to CQ\n mapping", "Date": "Wed, 10 Aug 2022 00:19:07 +0530", "Message-ID": "<20220809184908.24030-23-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220809184908.24030-1-ndabilpuram@marvell.com>", "References": "<20220809184908.24030-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "31dY_f6U8EgZR3_GsgiF97zPMRdqAHDT", "X-Proofpoint-GUID": "31dY_f6U8EgZR3_GsgiF97zPMRdqAHDT", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1\n definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Kommula Shiva Shankar <kshankar@marvell.com>\n\nThis patch adds RoC support for Tx completion events via\nRQ to CQ mapping.\n\nSigned-off-by: Kommula Shiva Shankar <kshankar@marvell.com>\n---\n drivers/common/cnxk/roc_nix.c | 5 ++++-\n drivers/common/cnxk/roc_nix.h | 2 ++\n drivers/common/cnxk/roc_nix_queue.c | 7 ++-----\n drivers/net/cnxk/cnxk_ethdev.c | 3 +++\n 4 files changed, 11 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c\nindex 151d8c3..4bb306b 100644\n--- a/drivers/common/cnxk/roc_nix.c\n+++ b/drivers/common/cnxk/roc_nix.c\n@@ -154,7 +154,10 @@ roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq,\n \t\treturn rc;\n \treq->rq_cnt = nb_rxq;\n \treq->sq_cnt = nb_txq;\n-\treq->cq_cnt = nb_rxq;\n+\tif (roc_nix->tx_compl_ena)\n+\t\treq->cq_cnt = nb_rxq + nb_txq;\n+\telse\n+\t\treq->cq_cnt = nb_rxq;\n \t/* XQESZ can be W64 or W16 */\n \treq->xqe_sz = NIX_XQESZ_W16;\n \treq->rss_sz = nix->reta_sz;\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 2fddb20..3366080 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -281,6 +281,7 @@ struct roc_nix_stats_queue {\n struct roc_nix_rq {\n \t/* Input parameters */\n \tuint16_t qid;\n+\tuint16_t cqid; /* Not valid when SSO is enabled */\n \tuint16_t bpf_id;\n \tuint64_t aura_handle;\n \tbool ipsech_ena;\n@@ -406,6 +407,7 @@ struct roc_nix {\n \tuint16_t max_sqb_count;\n \tenum roc_nix_rss_reta_sz reta_sz;\n \tbool enable_loop;\n+\tbool tx_compl_ena;\n \tbool hw_vlan_ins;\n \tuint8_t lock_rx_ctx;\n \tuint16_t sqb_slack;\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 6030332..405d9a8 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -268,7 +268,7 @@ nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,\n \t\taq->rq.good_utag = rq->tag_mask >> 24;\n \t\taq->rq.bad_utag = rq->tag_mask >> 24;\n \t\taq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0);\n-\t\taq->rq.cq = rq->qid;\n+\t\taq->rq.cq = rq->cqid;\n \t}\n \n \tif (rq->ipsech_ena)\n@@ -395,7 +395,7 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n \t\taq->rq.good_utag = rq->tag_mask >> 24;\n \t\taq->rq.bad_utag = rq->tag_mask >> 24;\n \t\taq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0);\n-\t\taq->rq.cq = rq->qid;\n+\t\taq->rq.cq = rq->cqid;\n \t}\n \n \tif (rq->ipsech_ena) {\n@@ -644,9 +644,6 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)\n \tif (cq == NULL)\n \t\treturn NIX_ERR_PARAM;\n \n-\tif (cq->qid >= nix->nb_rx_queues)\n-\t\treturn NIX_ERR_QUEUE_INVALID_RANGE;\n-\n \tqsize = nix_qsize_clampup(cq->nb_desc);\n \tcq->nb_desc = nix_qsize_to_val(qsize);\n \tcq->qmask = cq->nb_desc - 1;\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex f08a20f..eb562ec 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -606,6 +606,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t/* Setup ROC RQ */\n \trq = &dev->rqs[qid];\n \trq->qid = qid;\n+\trq->cqid = cq->qid;\n \trq->aura_handle = mp->pool_id;\n \trq->flow_tag_width = 32;\n \trq->sso_ena = false;\n@@ -1168,6 +1169,8 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)\n \tif (roc_nix_is_lbk(nix))\n \t\tnix->enable_loop = eth_dev->data->dev_conf.lpbk_mode;\n \n+\tnix->tx_compl_ena = 0;\n+\n \t/* Alloc a nix lf */\n \trc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg);\n \tif (rc) {\n", "prefixes": [ "23/23" ] }