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GET /api/patches/114770/?format=api
{ "id": 114770, "url": "http://patches.dpdk.org/api/patches/114770/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220809184908.24030-9-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220809184908.24030-9-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220809184908.24030-9-ndabilpuram@marvell.com", "date": "2022-08-09T18:48:53", "name": "[09/23] common/cnxk: update attributes to pools used by NIX", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "9fa7ce55ccf0672fdc1f94369e9641c7d58c30d6", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220809184908.24030-9-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 24239, "url": "http://patches.dpdk.org/api/series/24239/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24239", "date": "2022-08-09T18:48:45", "name": "[01/23] common/cnxk: fix part value for cn10k", "version": 1, "mbox": "http://patches.dpdk.org/series/24239/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/114770/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/114770/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4604AA04FD;\n\tTue, 9 Aug 2022 20:50:20 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3BA2242BED;\n\tTue, 9 Aug 2022 20:50:20 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id EA1FD42BE8\n for <dev@dpdk.org>; Tue, 9 Aug 2022 20:50:18 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 279D4IN4016373\n for <dev@dpdk.org>; Tue, 9 Aug 2022 11:50:18 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3huds2uktk-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 09 Aug 2022 11:50:18 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 9 Aug 2022 11:50:16 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 9 Aug 2022 11:50:16 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 4488D3F7122;\n Tue, 9 Aug 2022 11:50:06 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=68QCYvTk7stmxIFZjfuzR3Fs6wjw7yF2PliMMX+H7us=;\n b=kd07ebVadl92INtHhrPd/Dk9AM6PeLTTWsLy1bsl7UrPby313jnBZQzcK1Lxmk1yQCu/\n Aj//YE+pUtMP7Po8ZUIhxrgMchQsHjR1LFPPvHZv0XSOGG+yYkpxbwqkGJSMXm/kS5yF\n t3llo8oCL287Fl+KZPGyRJEEEb1oH1WfQjDOdeE8jXXQMwWRs3rdla+8WvHYPliW+BYW\n zOJHhoISG4exZd0XGI3c5N6Kf9oXjdj8qwp62AS1wh2KHSFa7R/iKwtxTjGniPwer/ab\n q1PG0SZfC2YQG+SRNlG4nFR/Shg/0n+FwSgGelCsnuzZu3XJbBZJYQBySdWDxt8sxBDW rg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 09/23] common/cnxk: update attributes to pools used by NIX", "Date": "Wed, 10 Aug 2022 00:18:53 +0530", "Message-ID": "<20220809184908.24030-9-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220809184908.24030-1-ndabilpuram@marvell.com>", "References": "<20220809184908.24030-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "2JxENP7ZGXUZJQuH4r9suE4ntU38wl9r", "X-Proofpoint-GUID": "2JxENP7ZGXUZJQuH4r9suE4ntU38wl9r", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1\n definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Update attributes to pools used by NIX.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix_queue.c | 112 +++++++++++++++++++++++++++++++++++-\n 1 file changed, 110 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 70b4516..98b9fb4 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -140,6 +140,96 @@ roc_nix_rq_is_sso_enable(struct roc_nix *roc_nix, uint32_t qid)\n \treturn sso_enable ? true : false;\n }\n \n+static int\n+nix_rq_aura_buf_type_update(struct roc_nix_rq *rq, bool set)\n+{\n+\tstruct roc_nix *roc_nix = rq->roc_nix;\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tbool inl_inb_ena = roc_nix_inl_inb_is_enabled(roc_nix);\n+\tuint64_t lpb_aura = 0, vwqe_aura = 0, spb_aura = 0;\n+\tstruct mbox *mbox = nix->dev.mbox;\n+\tuint64_t aura_base;\n+\tint rc, count;\n+\n+\tcount = set ? 1 : -1;\n+\t/* For buf type set, use info from RQ context */\n+\tif (set) {\n+\t\tlpb_aura = rq->aura_handle;\n+\t\tspb_aura = rq->spb_ena ? rq->spb_aura_handle : 0;\n+\t\tvwqe_aura = rq->vwqe_ena ? rq->vwqe_aura_handle : 0;\n+\t\tgoto skip_ctx_read;\n+\t}\n+\n+\taura_base = roc_npa_aura_handle_to_base(rq->aura_handle);\n+\tif (roc_model_is_cn9k()) {\n+\t\tstruct nix_aq_enq_rsp *rsp;\n+\t\tstruct nix_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n+\t\taq->qidx = rq->qid;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\t\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\t/* Get aura handle from aura */\n+\t\tlpb_aura = roc_npa_aura_handle_gen(rsp->rq.lpb_aura, aura_base);\n+\t\tif (rsp->rq.spb_ena)\n+\t\t\tspb_aura = roc_npa_aura_handle_gen(rsp->rq.spb_aura, aura_base);\n+\t} else {\n+\t\tstruct nix_cn10k_aq_enq_rsp *rsp;\n+\t\tstruct nix_cn10k_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n+\t\taq->qidx = rq->qid;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\n+\t\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\t/* Get aura handle from aura */\n+\t\tlpb_aura = roc_npa_aura_handle_gen(rsp->rq.lpb_aura, aura_base);\n+\t\tif (rsp->rq.spb_ena)\n+\t\t\tspb_aura = roc_npa_aura_handle_gen(rsp->rq.spb_aura, aura_base);\n+\t\tif (rsp->rq.vwqe_ena)\n+\t\t\tvwqe_aura = roc_npa_aura_handle_gen(rsp->rq.wqe_aura, aura_base);\n+\t}\n+\n+skip_ctx_read:\n+\t/* Update attributes for LPB aura */\n+\tif (inl_inb_ena)\n+\t\troc_npa_buf_type_update(lpb_aura, ROC_NPA_BUF_TYPE_PACKET_IPSEC, count);\n+\telse\n+\t\troc_npa_buf_type_update(lpb_aura, ROC_NPA_BUF_TYPE_PACKET, count);\n+\n+\t/* Update attributes for SPB aura */\n+\tif (spb_aura) {\n+\t\tif (inl_inb_ena)\n+\t\t\troc_npa_buf_type_update(spb_aura, ROC_NPA_BUF_TYPE_PACKET_IPSEC, count);\n+\t\telse\n+\t\t\troc_npa_buf_type_update(spb_aura, ROC_NPA_BUF_TYPE_PACKET, count);\n+\t}\n+\n+\t/* Update attributes for VWQE aura */\n+\tif (vwqe_aura) {\n+\t\tif (inl_inb_ena)\n+\t\t\troc_npa_buf_type_update(vwqe_aura, ROC_NPA_BUF_TYPE_VWQE_IPSEC, count);\n+\t\telse\n+\t\t\troc_npa_buf_type_update(vwqe_aura, ROC_NPA_BUF_TYPE_VWQE, count);\n+\t}\n+\n+\treturn 0;\n+}\n+\n int\n nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,\n \t\tbool cfg, bool ena)\n@@ -292,7 +382,7 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n \t\t\t/* Maximal Vector size is (2^(MAX_VSIZE_EXP+2)) */\n \t\t\taq->rq.max_vsize_exp = rq->vwqe_max_sz_exp - 2;\n \t\t\taq->rq.vtime_wait = rq->vwqe_wait_tmo;\n-\t\t\taq->rq.wqe_aura = rq->vwqe_aura_handle;\n+\t\t\taq->rq.wqe_aura = roc_npa_aura_handle_to_aura(rq->vwqe_aura_handle);\n \t\t}\n \t} else {\n \t\t/* CQ mode */\n@@ -463,6 +553,9 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \tif (rc)\n \t\treturn rc;\n \n+\t/* Update aura buf type to indicate its use */\n+\tnix_rq_aura_buf_type_update(rq, true);\n+\n \treturn nix_tel_node_add_rq(rq);\n }\n \n@@ -481,6 +574,9 @@ roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \tif (rq->qid >= nix->nb_rx_queues)\n \t\treturn NIX_ERR_QUEUE_INVALID_RANGE;\n \n+\t/* Clear attributes for existing aura's */\n+\tnix_rq_aura_buf_type_update(rq, false);\n+\n \trq->roc_nix = roc_nix;\n \n \tif (is_cn9k)\n@@ -495,14 +591,25 @@ roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \tif (rc)\n \t\treturn rc;\n \n+\t/* Update aura attribute to indicate its use */\n+\tnix_rq_aura_buf_type_update(rq, true);\n+\n \treturn nix_tel_node_add_rq(rq);\n }\n \n int\n roc_nix_rq_fini(struct roc_nix_rq *rq)\n {\n+\tint rc;\n+\n \t/* Disabling RQ is sufficient */\n-\treturn roc_nix_rq_ena_dis(rq, false);\n+\trc = roc_nix_rq_ena_dis(rq, false);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Update aura attribute to indicate its use for */\n+\tnix_rq_aura_buf_type_update(rq, false);\n+\treturn 0;\n }\n \n int\n@@ -717,6 +824,7 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)\n \tif (rc)\n \t\tgoto fail;\n \n+\troc_npa_buf_type_update(sq->aura_handle, ROC_NPA_BUF_TYPE_SQB, 1);\n \tsq->sqe_mem = plt_zmalloc(blk_sz * nb_sqb_bufs, blk_sz);\n \tif (sq->sqe_mem == NULL) {\n \t\trc = NIX_ERR_NO_MEM;\n", "prefixes": [ "09/23" ] }