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GET /api/patches/113042/?format=api
{ "id": 113042, "url": "http://patches.dpdk.org/api/patches/113042/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220618084805.87315-2-lizh@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220618084805.87315-2-lizh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220618084805.87315-2-lizh@nvidia.com", "date": "2022-06-18T08:47:51", "name": "[v3,01/15] vdpa/mlx5: fix usage of capability for max number of virtqs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "05eb31c4054db9fdb38df8fa76c38985b80399df", "submitter": { "id": 1967, "url": "http://patches.dpdk.org/api/people/1967/?format=api", "name": "Li Zhang", "email": "lizh@nvidia.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220618084805.87315-2-lizh@nvidia.com/mbox/", "series": [ { "id": 23621, "url": "http://patches.dpdk.org/api/series/23621/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23621", "date": "2022-06-18T08:47:50", "name": "mlx5/vdpa: optimize live migration time", "version": 3, "mbox": "http://patches.dpdk.org/series/23621/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/113042/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/113042/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C79C8A0032;\n\tSat, 18 Jun 2022 10:48:36 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BA5AE410E7;\n\tSat, 18 Jun 2022 10:48:36 +0200 (CEST)", "from NAM02-SN1-obe.outbound.protection.outlook.com\n (mail-sn1anam02on2044.outbound.protection.outlook.com [40.107.96.44])\n by mails.dpdk.org (Postfix) with ESMTP id B742A40E2D;\n Sat, 18 Jun 2022 10:48:34 +0200 (CEST)", "from DM5PR2001CA0001.namprd20.prod.outlook.com (2603:10b6:4:16::11)\n by BY5PR12MB3764.namprd12.prod.outlook.com (2603:10b6:a03:1ac::17)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5353.15; 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helo=mail.nvidia.com; pr=C", "From": "Li Zhang <lizh@nvidia.com>", "To": "<orika@nvidia.com>, <viacheslavo@nvidia.com>, <matan@nvidia.com>,\n <shahafs@nvidia.com>, Maxime Coquelin <maxime.coquelin@redhat.com>", "CC": "<dev@dpdk.org>, <thomas@monjalon.net>, <rasland@nvidia.com>,\n <roniba@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH v3 01/15] vdpa/mlx5: fix usage of capability for max number of\n virtqs", "Date": "Sat, 18 Jun 2022 11:47:51 +0300", "Message-ID": "<20220618084805.87315-2-lizh@nvidia.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220618084805.87315-1-lizh@nvidia.com>", "References": "<20220408075606.33056-1-lizh@nvidia.com>\n <20220618084805.87315-1-lizh@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "fab36f6a-134f-4e8a-8abd-08da51074f81", "X-MS-TrafficTypeDiagnostic": "BY5PR12MB3764:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BY5PR12MB3764BEEEF21CA261D99D71C5BFAE9@BY5PR12MB3764.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Y+3+boiVOiZnkCx14K5FD8xkJFy2/N0wpse2G3aUUwAwt3KDNVWwH7oD6g+h/FcxGZPfteIL+OjV+laWp72spma0pe9dalpatSiWtfrCgFmMFHjJ6KtZXJIGNWJenB4t3dx4ZUHXwjsorwbulXD/sva3DdEiPU4qsfJo/qrfmg7Hl9G4w1clfotjjXZqnC/hrIFMt1z3txQ5NgcYIbGlHqUjudKU+/TT5gNd1brx+LkyG8pUypBU3LDzh0O/bQe/cg6vvb9n5aIprF1h0FjCnIVYLDD75gCsGiNYij+7npbyzK4ssx02i1igBhny4/T579A4vEsfi8ZxomG8ERdEdcO+rSkFZPXVtBhhcM0B0XF3jpvbt3yGEjYYb6J2jNkomcZ4OQ166DLtSWEXA2vIHsJMwQL2PdTaHTL3oQ6jTmSkcXBtXdP5cpM6re8VjpouWLE7F9CLLU3gAY/SZi7yRiwMeUTwxClu8jdf5NRqafjVoFgx+H2VEczkxcBHLnDVDpdvbwbGJSJJRMg9+7NWXtpIyWwF/L9tPxekp6g3JgUufoNn2wloS+LBRom0dSRMJWTvvxMaqgni6gnCL3S/284QUvDKsluehxXtA+pjWQG3+3r3yBN//Hy5DvU3C4lzU4TfTe6WdX/rdsAvIjKMhfnwWByviWeEszdr08m0k2QDoiDo7pJZBnEsquHU1PzgBBaAqqx4nkuedqm2yU2eIg==", "X-Forefront-Antispam-Report": "CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230016)(4636009)(46966006)(40470700004)(36840700001)(83380400001)(186003)(47076005)(16526019)(336012)(2616005)(6286002)(426003)(26005)(1076003)(36860700001)(54906003)(356005)(110136005)(40460700003)(81166007)(316002)(86362001)(36756003)(82310400005)(5660300002)(7696005)(4326008)(8676002)(70586007)(70206006)(498600001)(2906002)(8936002)(55016003)(6666004)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Jun 2022 08:48:26.5607 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n fab36f6a-134f-4e8a-8abd-08da51074f81", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT017.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB3764", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The driver wrongly takes the capability value for\nthe number of virtq pairs instead of just the number of virtqs.\n\nAdjust all the usages of it to be the number of virtqs.\n\nFixes: c2eb33a (\"vdpa/mlx5: manage virtqs by array\")\nCc: stable@dpdk.org\n\nSigned-off-by: Li Zhang <lizh@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n drivers/vdpa/mlx5/mlx5_vdpa.c | 12 ++++++------\n drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 6 +++---\n 2 files changed, 9 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c\nindex 76fa5d4299..ee71339b78 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.c\n@@ -84,7 +84,7 @@ mlx5_vdpa_get_queue_num(struct rte_vdpa_device *vdev, uint32_t *queue_num)\n \t\tDRV_LOG(ERR, \"Invalid vDPA device: %s.\", vdev->device->name);\n \t\treturn -1;\n \t}\n-\t*queue_num = priv->caps.max_num_virtio_queues;\n+\t*queue_num = priv->caps.max_num_virtio_queues / 2;\n \treturn 0;\n }\n \n@@ -141,7 +141,7 @@ mlx5_vdpa_set_vring_state(int vid, int vring, int state)\n \t\tDRV_LOG(ERR, \"Invalid vDPA device: %s.\", vdev->device->name);\n \t\treturn -EINVAL;\n \t}\n-\tif (vring >= (int)priv->caps.max_num_virtio_queues * 2) {\n+\tif (vring >= (int)priv->caps.max_num_virtio_queues) {\n \t\tDRV_LOG(ERR, \"Too big vring id: %d.\", vring);\n \t\treturn -E2BIG;\n \t}\n@@ -388,7 +388,7 @@ mlx5_vdpa_get_stats(struct rte_vdpa_device *vdev, int qid,\n \t\tDRV_LOG(ERR, \"Invalid device: %s.\", vdev->device->name);\n \t\treturn -ENODEV;\n \t}\n-\tif (qid >= (int)priv->caps.max_num_virtio_queues * 2) {\n+\tif (qid >= (int)priv->caps.max_num_virtio_queues) {\n \t\tDRV_LOG(ERR, \"Too big vring id: %d for device %s.\", qid,\n \t\t\t\tvdev->device->name);\n \t\treturn -E2BIG;\n@@ -411,7 +411,7 @@ mlx5_vdpa_reset_stats(struct rte_vdpa_device *vdev, int qid)\n \t\tDRV_LOG(ERR, \"Invalid device: %s.\", vdev->device->name);\n \t\treturn -ENODEV;\n \t}\n-\tif (qid >= (int)priv->caps.max_num_virtio_queues * 2) {\n+\tif (qid >= (int)priv->caps.max_num_virtio_queues) {\n \t\tDRV_LOG(ERR, \"Too big vring id: %d for device %s.\", qid,\n \t\t\t\tvdev->device->name);\n \t\treturn -E2BIG;\n@@ -624,7 +624,7 @@ mlx5_vdpa_dev_probe(struct mlx5_common_device *cdev,\n \t\tDRV_LOG(DEBUG, \"No capability to support virtq statistics.\");\n \tpriv = rte_zmalloc(\"mlx5 vDPA device private\", sizeof(*priv) +\n \t\t\t sizeof(struct mlx5_vdpa_virtq) *\n-\t\t\t attr->vdpa.max_num_virtio_queues * 2,\n+\t\t\t attr->vdpa.max_num_virtio_queues,\n \t\t\t RTE_CACHE_LINE_SIZE);\n \tif (!priv) {\n \t\tDRV_LOG(ERR, \"Failed to allocate private memory.\");\n@@ -685,7 +685,7 @@ mlx5_vdpa_release_dev_resources(struct mlx5_vdpa_priv *priv)\n \tuint32_t i;\n \n \tmlx5_vdpa_dev_cache_clean(priv);\n-\tfor (i = 0; i < priv->caps.max_num_virtio_queues * 2; i++) {\n+\tfor (i = 0; i < priv->caps.max_num_virtio_queues; i++) {\n \t\tif (!priv->virtqs[i].counters)\n \t\t\tcontinue;\n \t\tclaim_zero(mlx5_devx_cmd_destroy(priv->virtqs[i].counters));\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\nindex e025be47d2..c258eb3024 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_virtq.c\n@@ -72,7 +72,7 @@ mlx5_vdpa_virtqs_cleanup(struct mlx5_vdpa_priv *priv)\n {\n \tunsigned int i, j;\n \n-\tfor (i = 0; i < priv->caps.max_num_virtio_queues * 2; i++) {\n+\tfor (i = 0; i < priv->caps.max_num_virtio_queues; i++) {\n \t\tstruct mlx5_vdpa_virtq *virtq = &priv->virtqs[i];\n \n \t\tfor (j = 0; j < RTE_DIM(virtq->umems); ++j) {\n@@ -492,9 +492,9 @@ mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv)\n \t\tDRV_LOG(INFO, \"TSO is enabled without CSUM, force CSUM.\");\n \t\tpriv->features |= (1ULL << VIRTIO_NET_F_CSUM);\n \t}\n-\tif (nr_vring > priv->caps.max_num_virtio_queues * 2) {\n+\tif (nr_vring > priv->caps.max_num_virtio_queues) {\n \t\tDRV_LOG(ERR, \"Do not support more than %d virtqs(%d).\",\n-\t\t\t(int)priv->caps.max_num_virtio_queues * 2,\n+\t\t\t(int)priv->caps.max_num_virtio_queues,\n \t\t\t(int)nr_vring);\n \t\treturn -1;\n \t}\n", "prefixes": [ "v3", "01/15" ] }