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GET /api/patches/112838/?format=api
{ "id": 112838, "url": "http://patches.dpdk.org/api/patches/112838/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220616070743.30658-9-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220616070743.30658-9-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220616070743.30658-9-ndabilpuram@marvell.com", "date": "2022-06-16T07:07:40", "name": "[09/12] net/cnxk: pfc class disable resulting in invalid behaviour", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "f9d1017c3cef3ba67f4fe7040a6df8e2353586ee", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220616070743.30658-9-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 23552, "url": "http://patches.dpdk.org/api/series/23552/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23552", "date": "2022-06-16T07:07:32", "name": "[01/12] common/cnxk: use computed value for wqe skip", "version": 1, "mbox": "http://patches.dpdk.org/series/23552/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/112838/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/112838/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 32533A00C3;\n\tThu, 16 Jun 2022 09:09:59 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2731C42BD1;\n\tThu, 16 Jun 2022 09:09:59 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id CCB0442BCA\n for <dev@dpdk.org>; Thu, 16 Jun 2022 09:09:57 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 25FN9p0V014305\n for <dev@dpdk.org>; Thu, 16 Jun 2022 00:09:57 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3gqruu9khf-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 16 Jun 2022 00:09:56 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 16 Jun 2022 00:09:55 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 16 Jun 2022 00:09:55 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 247363F703F;\n Thu, 16 Jun 2022 00:09:52 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=psjGFqjfwk3xpLtzmqCfyANN058bufBwdQgFS5iuVyg=;\n b=XS4ZgzU7AaczO/0bsOHwhSu0anqyOe9woITy5KhL3Ao6ntNdVSqOERoUTCTEWTKQ+nw5\n 6OyfY9P07PRBHrUlWMcWOOJm3emGN+bfOfaWFg11JL19M5aEL7djXH776VG2QZsQbsqT\n HIBE7FyTVtbfGc+wxmYw20df5i/Gxb5CkeoHeLdrPqvfVXq+3QtGO2/mdnAgkh5IqnkU\n zlaPymXxNed0GI7C88aj5RI+RjeWAeic1QmYmQZ1uIVvnATnbYzZ2jWytusla/j2qwms\n j13j+luNz7h/z/4dKJldyNLenaI/uZUlFcV9x7NFybfgsnwKHa29pM6pacN02QFlQ6Wa 3A==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Harman Kalra <hkalra@marvell.com>", "Subject": "[PATCH 09/12] net/cnxk: pfc class disable resulting in invalid\n behaviour", "Date": "Thu, 16 Jun 2022 12:37:40 +0530", "Message-ID": "<20220616070743.30658-9-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220616070743.30658-1-ndabilpuram@marvell.com>", "References": "<20220616070743.30658-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "ShwKdLdkyVQKDluP9wkwzexdJ3h0_wsc", "X-Proofpoint-GUID": "ShwKdLdkyVQKDluP9wkwzexdJ3h0_wsc", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514\n definitions=2022-06-16_03,2022-06-15_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Harman Kalra <hkalra@marvell.com>\n\nDisabling a specific pfc class on a SQ is resulting in disabling PFC\non the entire port.\n\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/net/cnxk/cnxk_ethdev.c | 25 ++++++++++++-------------\n drivers/net/cnxk/cnxk_ethdev.h | 1 -\n drivers/net/cnxk/cnxk_ethdev_ops.c | 34 +++++++++++++++++++++++++++-------\n 3 files changed, 39 insertions(+), 21 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 941b270..4ea1617 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -439,6 +439,7 @@ cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tsq->qid = qid;\n \tsq->nb_desc = nb_desc;\n \tsq->max_sqe_sz = nix_sq_max_sqe_sz(dev);\n+\tsq->tc = ROC_NIX_PFC_CLASS_INVALID;\n \n \trc = roc_nix_sq_init(&dev->nix, sq);\n \tif (rc) {\n@@ -1281,8 +1282,6 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)\n \t\tgoto cq_fini;\n \t}\n \n-\t/* Initialize TC to SQ mapping as invalid */\n-\tmemset(dev->pfc_tc_sq_map, 0xFF, sizeof(dev->pfc_tc_sq_map));\n \t/*\n \t * Restore queue config when reconfigure followed by\n \t * reconfigure and no queue configure invoked from application case.\n@@ -1794,17 +1793,17 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)\n \trc = cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf);\n \n \tpfc_conf.mode = RTE_ETH_FC_NONE;\n-\tfor (i = 0; i < CNXK_NIX_PFC_CHAN_COUNT; i++) {\n-\t\tif (dev->pfc_tc_sq_map[i] != 0xFFFF) {\n-\t\t\tpfc_conf.rx_pause.tx_qid = dev->pfc_tc_sq_map[i];\n-\t\t\tpfc_conf.rx_pause.tc = i;\n-\t\t\tpfc_conf.tx_pause.tc = i;\n-\t\t\trc = cnxk_nix_priority_flow_ctrl_queue_config(eth_dev,\n-\t\t\t\t&pfc_conf);\n-\t\t\tif (rc)\n-\t\t\t\tplt_err(\"Failed to reset PFC. error code(%d)\",\n-\t\t\t\t\trc);\n-\t\t}\n+\tfor (i = 0; i < RTE_MAX(eth_dev->data->nb_rx_queues,\n+\t\t\t\teth_dev->data->nb_tx_queues);\n+\t i++) {\n+\t\tpfc_conf.rx_pause.tc = ROC_NIX_PFC_CLASS_INVALID;\n+\t\tpfc_conf.rx_pause.tx_qid = i;\n+\t\tpfc_conf.tx_pause.tc = ROC_NIX_PFC_CLASS_INVALID;\n+\t\tpfc_conf.tx_pause.rx_qid = i;\n+\t\trc = cnxk_nix_priority_flow_ctrl_queue_config(eth_dev,\n+\t\t\t\t\t\t\t &pfc_conf);\n+\t\tif (rc)\n+\t\t\tplt_err(\"Failed to reset PFC. error code(%d)\", rc);\n \t}\n \n \t/* Disable and free rte_meter entries */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex db2d849..a4e96f0 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -396,7 +396,6 @@ struct cnxk_eth_dev {\n \tstruct cnxk_eth_qconf *rx_qconf;\n \n \t/* Flow control configuration */\n-\tuint16_t pfc_tc_sq_map[CNXK_NIX_PFC_CHAN_COUNT];\n \tstruct cnxk_pfc_cfg pfc_cfg;\n \tstruct cnxk_fc_cfg fc_cfg;\n \ndiff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c\nindex caace9d..1592971 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_ops.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c\n@@ -1129,8 +1129,10 @@ nix_priority_flow_ctrl_sq_conf(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tstruct rte_eth_dev_data *data = eth_dev->data;\n \tstruct cnxk_pfc_cfg *pfc = &dev->pfc_cfg;\n \tstruct roc_nix *nix = &dev->nix;\n+\tstruct roc_nix_pfc_cfg pfc_cfg;\n \tstruct roc_nix_fc_cfg fc_cfg;\n \tstruct cnxk_eth_txq_sp *txq;\n+\tenum roc_nix_fc_mode mode;\n \tstruct roc_nix_sq *sq;\n \tint rc;\n \n@@ -1140,12 +1142,6 @@ nix_priority_flow_ctrl_sq_conf(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tif (qid >= eth_dev->data->nb_tx_queues)\n \t\treturn -ENOTSUP;\n \n-\tif (dev->pfc_tc_sq_map[tc] != 0xFFFF &&\n-\t dev->pfc_tc_sq_map[tc] != qid) {\n-\t\tplt_err(\"Same TC can not be configured on multiple SQs\");\n-\t\treturn -ENOTSUP;\n-\t}\n-\n \t/* Check if RX pause frame is enabled or not */\n \tif (!pfc->rx_pause_en) {\n \t\tif ((roc_nix_tm_tree_type_get(nix) == ROC_NIX_TM_DEFAULT) &&\n@@ -1180,7 +1176,31 @@ nix_priority_flow_ctrl_sq_conf(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tif (rc)\n \t\treturn rc;\n \n-\tdev->pfc_tc_sq_map[tc] = sq->qid;\n+\t/* Maintaining a count for SQs which are configured for PFC. This is\n+\t * required to handle disabling of a particular SQ without affecting\n+\t * PFC on other SQs.\n+\t */\n+\tif (!fc_cfg.tm_cfg.enable && sq->tc != ROC_NIX_PFC_CLASS_INVALID) {\n+\t\tsq->tc = ROC_NIX_PFC_CLASS_INVALID;\n+\t\tpfc->rx_pause_en--;\n+\t} else if (fc_cfg.tm_cfg.enable &&\n+\t\t sq->tc == ROC_NIX_PFC_CLASS_INVALID) {\n+\t\tsq->tc = tc;\n+\t\tpfc->rx_pause_en++;\n+\t}\n+\n+\tif (pfc->rx_pause_en > 1)\n+\t\tgoto exit;\n+\n+\tif (pfc->tx_pause_en)\n+\t\tmode = pfc->rx_pause_en ? ROC_NIX_FC_FULL : ROC_NIX_FC_TX;\n+\telse\n+\t\tmode = pfc->rx_pause_en ? ROC_NIX_FC_RX : ROC_NIX_FC_NONE;\n+\n+\tmemset(&pfc_cfg, 0, sizeof(struct roc_nix_pfc_cfg));\n+\tpfc_cfg.mode = mode;\n+\tpfc_cfg.tc = pfc->class_en;\n+\trc = roc_nix_pfc_mode_set(nix, &pfc_cfg);\n exit:\n \treturn rc;\n }\n", "prefixes": [ "09/12" ] }