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GET /api/patches/112766/?format=api
{ "id": 112766, "url": "http://patches.dpdk.org/api/patches/112766/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220615125836.391771-6-spiked@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220615125836.391771-6-spiked@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220615125836.391771-6-spiked@nvidia.com", "date": "2022-06-15T12:58:35", "name": "[v8,5/6] net/mlx5: add private API to config host port shaper", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a1a5be998b9f17cf38bfb4d9e2247773829c712e", "submitter": { "id": 2637, "url": "http://patches.dpdk.org/api/people/2637/?format=api", "name": "Spike Du", "email": "spiked@nvidia.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220615125836.391771-6-spiked@nvidia.com/mbox/", "series": [ { "id": 23538, "url": "http://patches.dpdk.org/api/series/23538/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23538", "date": "2022-06-15T12:58:30", "name": "introduce per-queue available descriptor threshold and host shaper", "version": 8, "mbox": "http://patches.dpdk.org/series/23538/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/112766/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/112766/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B6546A0548;\n\tWed, 15 Jun 2022 15:09:20 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EB5FA427F1;\n\tWed, 15 Jun 2022 15:09:10 +0200 (CEST)", "from NAM02-DM3-obe.outbound.protection.outlook.com\n (mail-dm3nam02on2069.outbound.protection.outlook.com [40.107.95.69])\n by mails.dpdk.org (Postfix) with ESMTP id CC83942905\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Spike Du <spiked@nvidia.com>", "To": "<matan@nvidia.com>, <viacheslavo@nvidia.com>, <orika@nvidia.com>,\n <thomas@monjalon.net>, Shahaf Shuler <shahafs@nvidia.com>, Ray Kinsella\n <mdr@ashroe.eu>, Neil Horman <nhorman@tuxdriver.com>", "CC": "<andrew.rybchenko@oktetlabs.ru>, <stephen@networkplumber.org>,\n <mb@smartsharesystems.com>, <dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH v8 5/6] net/mlx5: add private API to config host port shaper", "Date": "Wed, 15 Jun 2022 15:58:35 +0300", "Message-ID": "<20220615125836.391771-6-spiked@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20220615125836.391771-1-spiked@nvidia.com>", "References": "<20220614120134.1828188-2-spiked@nvidia.com>\n <20220615125836.391771-1-spiked@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "22c96a7d-99d0-49ec-239d-08da4eced7b8", "X-MS-TrafficTypeDiagnostic": "BN8PR12MB2993:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BN8PR12MB2993EC052078E541D0292A01A8AD9@BN8PR12MB2993.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n DnVweSIp0w1+E6YgxNGjnUfHC2o4/qS/nxGwmPjlXHK4LCG9UZ5Y7UsItb5De5EJa1TzZQUInEeBxdBounWYqCz6LqipGXzRHm3tlpuCS7LFeQ8xXKUhLy+WgYNBtFRujtTs8M9HUWS1w4eIT1VbfrzhN8rYgVZvIYEpZTrSgRrf41lza9zL8gckZBH4GUiwAl023TAg1JD3r4prduUoGJAVHjIcX3zWi9cUXE1LGMfoNokh5eL1bhKvddZZ0KAJkbNn4EMOMS3M1ItxK0tTMuZGmD/nSl/dYbeO3Md9S81vI7pudAvd5hgJzOPxbqzB+NsMgV88dcbG74ZY46yBObvJJogBN+F6q0waGBqouXHhzrcg3OVO+DI9fCx2jKqDcg+EW0yfD2t0TP0u/7Yw3mY2ktYjo9XAEiKLKsPFXcJxU3j0ducisxip7oD3SR1yetrRTRthlP75JDAbqbtwaMfSa6a9gGKJ1HRS6RawZ0QkbZznpQVel9MrEaT16LN5+rtRTMQjNUogojXlJmuyPvjnsVsUzp5nIb6bv7T1Ez+mJUPn1/n2TwfIRtyoPS5boYuwjYEPHqftWRlk+wKg11w1cWIfszmRBDsN8cbhpr1Q3N3fcdpkl1Hg75K8duw8MFZKs1lKq9QEvMSBVFXzW89ZKxuR6CrU4B1JinEsijKmvZrfEOqxi9SnbGl617uWmarsHef6fUtAbrZwWRo5dw==", "X-Forefront-Antispam-Report": "CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230016)(4636009)(40470700004)(36840700001)(46966006)(316002)(2906002)(508600001)(30864003)(4326008)(26005)(8936002)(110136005)(2616005)(5660300002)(70586007)(6286002)(36756003)(86362001)(54906003)(8676002)(70206006)(82310400005)(55016003)(83380400001)(47076005)(336012)(186003)(426003)(7696005)(6666004)(356005)(16526019)(1076003)(81166007)(40460700003)(107886003)(36860700001)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Jun 2022 12:59:11.4182 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 22c96a7d-99d0-49ec-239d-08da4eced7b8", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT029.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN8PR12MB2993", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Host port shaper can be configured with QSHR(QoS Shaper Host Register).\nAdd check in build files to enable this function or not.\n\nThe host shaper configuration affects all the ethdev ports belonging to the\nsame host port.\n\nHost shaper can configure shaper rate and lwm-triggered for a host port.\nThe shaper limits the rate of traffic from host port to wire port.\nIf lwm-triggered is enabled, a 100Mbps shaper is enabled automatically\nwhen one of the host port's Rx queues receives available descriptor\nthreshold event.\n\nSigned-off-by: Spike Du <spiked@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 35 +++++++++++\n doc/guides/rel_notes/release_22_07.rst | 1 +\n drivers/common/mlx5/linux/meson.build | 13 +++++\n drivers/common/mlx5/mlx5_prm.h | 25 ++++++++\n drivers/net/mlx5/mlx5.h | 2 +\n drivers/net/mlx5/mlx5_rx.c | 104 +++++++++++++++++++++++++++++++++\n drivers/net/mlx5/rte_pmd_mlx5.h | 30 ++++++++++\n drivers/net/mlx5/version.map | 2 +\n 8 files changed, 212 insertions(+)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex cceaddf..5f7b060 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -94,6 +94,7 @@ Features\n - Sub-Function representors.\n - Sub-Function.\n - Rx queue available descriptor threshold configuration.\n+- Host shaper support.\n \n \n Limitations\n@@ -525,6 +526,12 @@ Limitations\n \n - Doesn't support shared Rx queue and Hairpin Rx queue.\n \n+- Host shaper:\n+\n+ - Support BlueField series NIC from BlueField 2.\n+ - When configure host shaper with MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED flag set,\n+ only rate 0 and 100Mbps are supported.\n+\n Statistics\n ----------\n \n@@ -1692,3 +1699,31 @@ Available descriptor threshold is a per Rx queue attribute, it should be configu\n a percentage of the Rx queue size.\n When Rx queue available descriptors for hardware are below the threshold, an event is sent to PMD.\n \n+Host shaper introduction\n+------------------------\n+\n+Host shaper register is per host port register which sets a shaper\n+on the host port.\n+All VF/hostPF representors belonging to one host port share one host shaper.\n+For example, if representor 0 and representor 1 belong to same host port,\n+and a host shaper rate of 1Gbps is configured, the shaper throttles both\n+representors' traffic from host.\n+Host shaper has two modes for setting the shaper, immediate and deferred to\n+available descriptor threshold event trigger. In immediate mode, the rate limit is configured\n+immediately to host shaper. When deferring to available descriptor threshold trigger, the shaper\n+is not set until an available descriptor threshold event is received by any Rx queue in a VF\n+representor belonging to the host port. The only rate supported for deferred\n+mode is 100Mbps (there is no limit on the supported rates for immediate mode).\n+In deferred mode, the shaper is set on the host port by the firmware upon\n+receiving the available descriptor threshold event, which allows throttling host traffic on\n+available descriptor threshold events at minimum latency, preventing excess drops in the\n+Rx queue.\n+\n+Host shaper dependency for mstflint package\n+-------------------------------------------\n+\n+In order to configure host shaper register, ``librte_net_mlx5`` depends on ``libmtcr_ul``\n+which can be installed from OFED mstflint package.\n+Meson detects ``libmtcr_ul`` existence at configure stage.\n+If the library is detected, the application must link with ``-lmtcr_ul``,\n+as done by the pkg-config file libdpdk.pc.\ndiff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst\nindex 46fd73a..3349cda 100644\n--- a/doc/guides/rel_notes/release_22_07.rst\n+++ b/doc/guides/rel_notes/release_22_07.rst\n@@ -90,6 +90,7 @@ New Features\n * Added support for MTU on Windows.\n * Added matching and RSS on IPsec ESP.\n * Added Rx queue available descriptor threshold support.\n+ * Added host shaper support.\n \n * **Updated Marvell cnxk crypto driver.**\n \ndiff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build\nindex 5335f5b..51c6e5d 100644\n--- a/drivers/common/mlx5/linux/meson.build\n+++ b/drivers/common/mlx5/linux/meson.build\n@@ -45,6 +45,13 @@ if static_ibverbs\n ext_deps += declare_dependency(link_args:ibv_ldflags.split())\n endif\n \n+libmtcr_ul_found = false\n+lib = cc.find_library('mtcr_ul', required:false)\n+if lib.found() and run_command('meson', '--version').stdout().version_compare('>= 0.49.2')\n+ libmtcr_ul_found = true\n+ ext_deps += lib\n+endif\n+\n sources += files('mlx5_nl.c')\n sources += files('mlx5_common_auxiliary.c')\n sources += files('mlx5_common_os.c')\n@@ -207,6 +214,12 @@ has_sym_args = [\n [ 'HAVE_MLX5_IBV_IMPORT_CTX_PD_AND_MR', 'infiniband/verbs.h',\n 'ibv_import_device' ],\n ]\n+if libmtcr_ul_found\n+ has_sym_args += [\n+ [ 'HAVE_MLX5_MSTFLINT', 'mstflint/mtcr.h',\n+ 'mopen'],\n+ ]\n+endif\n config = configuration_data()\n foreach arg:has_sym_args\n config.set(arg[0], cc.has_header_symbol(arg[1], arg[2], dependencies: libs))\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 3b5e605..92d05a7 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3771,6 +3771,7 @@ enum {\n \tMLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,\n \tMLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,\n \tMLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,\n+\tMLX5_QSHR_REGISTER_ID = 0x4030,\n };\n \n struct mlx5_ifc_register_mtutc_bits {\n@@ -3785,6 +3786,30 @@ struct mlx5_ifc_register_mtutc_bits {\n \tu8 time_adjustment[0x20];\n };\n \n+struct mlx5_ifc_ets_global_config_register_bits {\n+\tu8 reserved_at_0[0x2];\n+\tu8 rate_limit_update[0x1];\n+\tu8 reserved_at_3[0x29];\n+\tu8 max_bw_units[0x4];\n+\tu8 reserved_at_48[0x8];\n+\tu8 max_bw_value[0x8];\n+};\n+\n+#define ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED 0x0\n+#define ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS 0x3\n+#define ETS_GLOBAL_CONFIG_BW_UNIT_GBPS 0x4\n+\n+struct mlx5_ifc_register_qshr_bits {\n+\tu8 reserved_at_0[0x4];\n+\tu8 connected_host[0x1];\n+\tu8 vqos[0x1];\n+\tu8 fast_response[0x1];\n+\tu8 reserved_at_7[0x1];\n+\tu8 local_port[0x8];\n+\tu8 reserved_at_16[0x230];\n+\tstruct mlx5_ifc_ets_global_config_register_bits global_config;\n+};\n+\n #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0\n #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1\n \ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex a76f2fe..8af84ae 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1271,6 +1271,8 @@ struct mlx5_dev_ctx_shared {\n \tvoid *devx_channel_lwm;\n \tstruct rte_intr_handle *intr_handle_lwm;\n \tpthread_mutex_t lwm_config_lock;\n+\tuint32_t host_shaper_rate:8;\n+\tuint32_t lwm_triggered:1;\n \t/* Availability of mreg_c's. */\n \tstruct mlx5_dev_shared_port port[]; /* per device port data array. */\n };\ndiff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c\nindex 2cb7006..bb3ccc3 100644\n--- a/drivers/net/mlx5/mlx5_rx.c\n+++ b/drivers/net/mlx5/mlx5_rx.c\n@@ -19,6 +19,7 @@\n #include <mlx5_prm.h>\n #include <mlx5_common.h>\n #include <mlx5_common_mr.h>\n+#include <rte_pmd_mlx5.h>\n \n #include \"mlx5_autoconf.h\"\n #include \"mlx5_defs.h\"\n@@ -27,6 +28,9 @@\n #include \"mlx5_rxtx.h\"\n #include \"mlx5_devx.h\"\n #include \"mlx5_rx.h\"\n+#ifdef HAVE_MLX5_MSTFLINT\n+#include <mstflint/mtcr.h>\n+#endif\n \n \n static __rte_always_inline uint32_t\n@@ -1371,3 +1375,103 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)\n \treturn ret;\n }\n \n+/**\n+ * Mlx5 access register function to configure host shaper.\n+ * It calls API in libmtcr_ul to access QSHR(Qos Shaper Host Register)\n+ * in firmware.\n+ *\n+ * @param dev\n+ * Pointer to rte_eth_dev.\n+ * @param lwm_triggered\n+ * Flag to enable/disable lwm_triggered bit in QSHR.\n+ * @param rate\n+ * Host shaper rate, unit is 100Mbps, set to 0 means disable the shaper.\n+ * @return\n+ * 0 : operation success.\n+ * Otherwise:\n+ * - ENOENT - no ibdev interface.\n+ * - EBUSY - the register access unit is busy.\n+ * - EIO - the register access command meets IO error.\n+ */\n+static int\n+mlxreg_host_shaper_config(struct rte_eth_dev *dev,\n+\t\t\t bool lwm_triggered, uint8_t rate)\n+{\n+#ifdef HAVE_MLX5_MSTFLINT\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tuint32_t data[MLX5_ST_SZ_DW(register_qshr)] = {0};\n+\tint rc, retry_count = 3;\n+\tmfile *mf = NULL;\n+\tint status;\n+\tvoid *ptr;\n+\n+\tmf = mopen(priv->sh->ibdev_name);\n+\tif (!mf) {\n+\t\tDRV_LOG(WARNING, \"mopen failed\\n\");\n+\t\trte_errno = ENOENT;\n+\t\treturn -rte_errno;\n+\t}\n+\tMLX5_SET(register_qshr, data, connected_host, 1);\n+\tMLX5_SET(register_qshr, data, fast_response, lwm_triggered ? 1 : 0);\n+\tMLX5_SET(register_qshr, data, local_port, 1);\n+\tptr = MLX5_ADDR_OF(register_qshr, data, global_config);\n+\tMLX5_SET(ets_global_config_register, ptr, rate_limit_update, 1);\n+\tMLX5_SET(ets_global_config_register, ptr, max_bw_units,\n+\t\t rate ? ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS :\n+\t\t ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED);\n+\tMLX5_SET(ets_global_config_register, ptr, max_bw_value, rate);\n+\tdo {\n+\t\trc = maccess_reg(mf,\n+\t\t\t\t MLX5_QSHR_REGISTER_ID,\n+\t\t\t\t MACCESS_REG_METHOD_SET,\n+\t\t\t\t (u_int32_t *)&data[0],\n+\t\t\t\t sizeof(data),\n+\t\t\t\t sizeof(data),\n+\t\t\t\t sizeof(data),\n+\t\t\t\t &status);\n+\t\tif ((rc != ME_ICMD_STATUS_IFC_BUSY &&\n+\t\t status != ME_REG_ACCESS_BAD_PARAM) ||\n+\t\t !(mf->flags & MDEVS_REM)) {\n+\t\t\tbreak;\n+\t\t}\n+\t\tDRV_LOG(WARNING, \"%s retry.\", __func__);\n+\t\tusleep(10000);\n+\t} while (retry_count-- > 0);\n+\tmclose(mf);\n+\trte_errno = (rc == ME_REG_ACCESS_DEV_BUSY) ? EBUSY : EIO;\n+\treturn rc ? -rte_errno : 0;\n+#else\n+\t(void)dev;\n+\t(void)lwm_triggered;\n+\t(void)rate;\n+\treturn -1;\n+#endif\n+}\n+\n+int rte_pmd_mlx5_host_shaper_config(int port_id, uint8_t rate,\n+\t\t\t\t uint32_t flags)\n+{\n+\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tbool lwm_triggered =\n+\t !!(flags & RTE_BIT32(MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED));\n+\n+\tif (!lwm_triggered) {\n+\t\tpriv->sh->host_shaper_rate = rate;\n+\t} else {\n+\t\tswitch (rate) {\n+\t\tcase 0:\n+\t\t/* Rate 0 means disable lwm_triggered. */\n+\t\t\tpriv->sh->lwm_triggered = 0;\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t/* Rate 1 means enable lwm_triggered. */\n+\t\t\tpriv->sh->lwm_triggered = 1;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -ENOTSUP;\n+\t\t}\n+\t}\n+\treturn mlxreg_host_shaper_config(dev, priv->sh->lwm_triggered,\n+\t\t\t\t\t priv->sh->host_shaper_rate);\n+}\ndiff --git a/drivers/net/mlx5/rte_pmd_mlx5.h b/drivers/net/mlx5/rte_pmd_mlx5.h\nindex 6e7907e..fbfdd97 100644\n--- a/drivers/net/mlx5/rte_pmd_mlx5.h\n+++ b/drivers/net/mlx5/rte_pmd_mlx5.h\n@@ -109,6 +109,36 @@ int rte_pmd_mlx5_external_rx_queue_id_map(uint16_t port_id, uint16_t dpdk_idx,\n int rte_pmd_mlx5_external_rx_queue_id_unmap(uint16_t port_id,\n \t\t\t\t\t uint16_t dpdk_idx);\n \n+/**\n+ * The rate of the host port shaper will be updated directly at the next\n+ * available descriptor threshold event to the rate that comes with this flag set;\n+ * set rate 0 to disable this rate update.\n+ * Unset this flag to update the rate of the host port shaper directly in\n+ * the API call; use rate 0 to disable the current shaper.\n+ */\n+#define MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED 0\n+\n+/**\n+ * Configure a HW shaper to limit Tx rate for a host port.\n+ * The configuration will affect all the ethdev ports belonging to\n+ * the same rte_device.\n+ *\n+ * @param[in] port_id\n+ * The port identifier of the Ethernet device.\n+ * @param[in] rate\n+ * Unit is 100Mbps, setting the rate to 0 disables the shaper.\n+ * @param[in] flags\n+ * Host shaper flags.\n+ * @return\n+ * 0 : operation success.\n+ * Otherwise:\n+ * - ENOENT - no ibdev interface.\n+ * - EBUSY - the register access unit is busy.\n+ * - EIO - the register access command meets IO error.\n+ */\n+__rte_experimental\n+int rte_pmd_mlx5_host_shaper_config(int port_id, uint8_t rate, uint32_t flags);\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/drivers/net/mlx5/version.map b/drivers/net/mlx5/version.map\nindex 79cb79a..c97dfe4 100644\n--- a/drivers/net/mlx5/version.map\n+++ b/drivers/net/mlx5/version.map\n@@ -12,4 +12,6 @@ EXPERIMENTAL {\n \t# added in 22.03\n \trte_pmd_mlx5_external_rx_queue_id_map;\n \trte_pmd_mlx5_external_rx_queue_id_unmap;\n+\t# added in 22.07\n+\trte_pmd_mlx5_host_shaper_config;\n };\n", "prefixes": [ "v8", "5/6" ] }