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{
    "id": 112413,
    "url": "http://patches.dpdk.org/api/patches/112413/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220606131054.2097526-2-zhoumin@loongson.cn/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220606131054.2097526-2-zhoumin@loongson.cn>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220606131054.2097526-2-zhoumin@loongson.cn",
    "date": "2022-06-06T13:10:31",
    "name": "[v3,01/24] eal/loongarch: add atomic operations for LoongArch",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "1062c2f9969b13632b098f6c21d9b78ed0d3cbd8",
    "submitter": {
        "id": 2394,
        "url": "http://patches.dpdk.org/api/people/2394/?format=api",
        "name": "zhoumin",
        "email": "zhoumin@loongson.cn"
    },
    "delegate": {
        "id": 24651,
        "url": "http://patches.dpdk.org/api/users/24651/?format=api",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220606131054.2097526-2-zhoumin@loongson.cn/mbox/",
    "series": [
        {
            "id": 23356,
            "url": "http://patches.dpdk.org/api/series/23356/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23356",
            "date": "2022-06-06T13:10:37",
            "name": "Support LoongArch architecture",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/23356/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/112413/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/112413/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D64A7A0542;\n\tMon,  6 Jun 2022 15:30:04 +0200 (CEST)",
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        ],
        "From": "Min Zhou <zhoumin@loongson.cn>",
        "To": "thomas@monjalon.net, david.marchand@redhat.com,\n bruce.richardson@intel.com,\n anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com,\n jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru",
        "Cc": "dev@dpdk.org,\n\tmaobibo@loongson.cn",
        "Subject": "[v3 01/24] eal/loongarch: add atomic operations for LoongArch",
        "Date": "Mon,  6 Jun 2022 21:10:31 +0800",
        "Message-Id": "<20220606131054.2097526-2-zhoumin@loongson.cn>",
        "X-Mailer": "git-send-email 2.31.1",
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    },
    "content": "This patch adds architecture specific atomic operations for\nLoongArch architecture. These implementations use standard atomics\nof toolchain and heavily reference generic atomics codes.\n\nSigned-off-by: Min Zhou <zhoumin@loongson.cn>\n---\n lib/eal/loongarch/include/rte_atomic.h | 253 +++++++++++++++++++++++++\n 1 file changed, 253 insertions(+)\n create mode 100644 lib/eal/loongarch/include/rte_atomic.h",
    "diff": "diff --git a/lib/eal/loongarch/include/rte_atomic.h b/lib/eal/loongarch/include/rte_atomic.h\nnew file mode 100644\nindex 0000000000..8e007e7f76\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_atomic.h\n@@ -0,0 +1,253 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef _RTE_ATOMIC_LOONGARCH_H_\n+#define _RTE_ATOMIC_LOONGARCH_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <stdint.h>\n+#include \"generic/rte_atomic.h\"\n+\n+/**\n+ * LoongArch Synchronize\n+ */\n+static inline void synchronize(void)\n+{\n+\t__asm__ __volatile__(\"dbar 0\":::\"memory\");\n+}\n+\n+/**\n+ * General memory barrier.\n+ *\n+ * Guarantees that the LOAD and STORE operations generated before the\n+ * barrier occur before the LOAD and STORE operations generated after.\n+ * This function is architecture dependent.\n+ */\n+#define rte_mb() synchronize()\n+\n+/**\n+ * Write memory barrier.\n+ *\n+ * Guarantees that the STORE operations generated before the barrier\n+ * occur before the STORE operations generated after.\n+ * This function is architecture dependent.\n+ */\n+#define rte_wmb() synchronize()\n+\n+/**\n+ * Read memory barrier.\n+ *\n+ * Guarantees that the LOAD operations generated before the barrier\n+ * occur before the LOAD operations generated after.\n+ * This function is architecture dependent.\n+ */\n+#define rte_rmb() synchronize()\n+\n+#define rte_smp_mb() rte_mb()\n+\n+#define rte_smp_wmb() rte_mb()\n+\n+#define rte_smp_rmb() rte_mb()\n+\n+#define rte_io_mb() rte_mb()\n+\n+#define rte_io_wmb() rte_mb()\n+\n+#define rte_io_rmb() rte_mb()\n+\n+static __rte_always_inline void\n+rte_atomic_thread_fence(int memorder)\n+{\n+\t__atomic_thread_fence(memorder);\n+}\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+/*------------------------- 16 bit atomic operations -------------------------*/\n+static inline int\n+rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)\n+{\n+\treturn __sync_bool_compare_and_swap(dst, exp, src);\n+}\n+\n+static inline uint16_t\n+rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)\n+{\n+#if defined(__clang__)\n+\treturn __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST);\n+#else\n+\treturn __atomic_exchange_2(dst, val, __ATOMIC_SEQ_CST);\n+#endif\n+}\n+\n+static inline void\n+rte_atomic16_inc(rte_atomic16_t *v)\n+{\n+\trte_atomic16_add(v, 1);\n+}\n+\n+static inline void\n+rte_atomic16_dec(rte_atomic16_t *v)\n+{\n+\trte_atomic16_sub(v, 1);\n+}\n+\n+static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)\n+{\n+\treturn __sync_add_and_fetch(&v->cnt, 1) == 0;\n+}\n+\n+static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)\n+{\n+\treturn __sync_sub_and_fetch(&v->cnt, 1) == 0;\n+}\n+\n+static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)\n+{\n+\treturn rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);\n+}\n+\n+/*------------------------- 32 bit atomic operations -------------------------*/\n+static inline int\n+rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)\n+{\n+\treturn __sync_bool_compare_and_swap(dst, exp, src);\n+}\n+\n+static inline uint32_t\n+rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)\n+{\n+#if defined(__clang__)\n+\treturn __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST);\n+#else\n+\treturn __atomic_exchange_4(dst, val, __ATOMIC_SEQ_CST);\n+#endif\n+}\n+\n+static inline void\n+rte_atomic32_inc(rte_atomic32_t *v)\n+{\n+\trte_atomic32_add(v, 1);\n+}\n+\n+static inline void\n+rte_atomic32_dec(rte_atomic32_t *v)\n+{\n+\trte_atomic32_sub(v, 1);\n+}\n+\n+static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)\n+{\n+\treturn __sync_add_and_fetch(&v->cnt, 1) == 0;\n+}\n+\n+static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)\n+{\n+\treturn __sync_sub_and_fetch(&v->cnt, 1) == 0;\n+}\n+\n+static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)\n+{\n+\treturn rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);\n+}\n+\n+/*------------------------- 64 bit atomic operations -------------------------*/\n+static inline int\n+rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)\n+{\n+\treturn __sync_bool_compare_and_swap(dst, exp, src);\n+}\n+\n+static inline uint64_t\n+rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)\n+{\n+#if defined(__clang__)\n+\treturn __atomic_exchange_n(dst, val, __ATOMIC_SEQ_CST);\n+#else\n+\treturn __atomic_exchange_8(dst, val, __ATOMIC_SEQ_CST);\n+#endif\n+}\n+\n+static inline void\n+rte_atomic64_init(rte_atomic64_t *v)\n+{\n+\tv->cnt = 0;\n+}\n+\n+static inline int64_t\n+rte_atomic64_read(rte_atomic64_t *v)\n+{\n+\treturn v->cnt;\n+}\n+\n+static inline void\n+rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)\n+{\n+\tv->cnt = new_value;\n+}\n+\n+static inline void\n+rte_atomic64_add(rte_atomic64_t *v, int64_t inc)\n+{\n+\t__sync_fetch_and_add(&v->cnt, inc);\n+}\n+\n+static inline void\n+rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)\n+{\n+\t__sync_fetch_and_sub(&v->cnt, dec);\n+}\n+\n+static inline void\n+rte_atomic64_inc(rte_atomic64_t *v)\n+{\n+\trte_atomic64_add(v, 1);\n+}\n+\n+static inline void\n+rte_atomic64_dec(rte_atomic64_t *v)\n+{\n+\trte_atomic64_sub(v, 1);\n+}\n+\n+static inline int64_t\n+rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)\n+{\n+\treturn __sync_add_and_fetch(&v->cnt, inc);\n+}\n+\n+static inline int64_t\n+rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)\n+{\n+\treturn __sync_sub_and_fetch(&v->cnt, dec);\n+}\n+\n+static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)\n+{\n+\treturn rte_atomic64_add_return(v, 1) == 0;\n+}\n+\n+static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)\n+{\n+\treturn rte_atomic64_sub_return(v, 1) == 0;\n+}\n+\n+static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)\n+{\n+\treturn rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);\n+}\n+\n+static inline void rte_atomic64_clear(rte_atomic64_t *v)\n+{\n+\trte_atomic64_set(v, 0);\n+}\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_ATOMIC_LOONGARCH_H_ */\n",
    "prefixes": [
        "v3",
        "01/24"
    ]
}