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GET /api/patches/112325/?format=api
{ "id": 112325, "url": "http://patches.dpdk.org/api/patches/112325/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220604163157.3509505-1-tduszynski@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220604163157.3509505-1-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220604163157.3509505-1-tduszynski@marvell.com", "date": "2022-06-04T16:31:57", "name": "common/cnxk: allow building generic arm64 target for cn9k/cn10k", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "69d311190d0a89a618c6c93dc02f659d655832f3", "submitter": { "id": 2215, "url": "http://patches.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220604163157.3509505-1-tduszynski@marvell.com/mbox/", "series": [ { "id": 23326, "url": "http://patches.dpdk.org/api/series/23326/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23326", "date": "2022-06-04T16:31:57", "name": "common/cnxk: allow building generic arm64 target for cn9k/cn10k", "version": 1, "mbox": "http://patches.dpdk.org/series/23326/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/112325/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/112325/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0E3ADA034C;\n\tSat, 4 Jun 2022 18:32:16 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EA02B4021E;\n\tSat, 4 Jun 2022 18:32:15 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 7E4BD40041\n for <dev@dpdk.org>; Sat, 4 Jun 2022 18:32:14 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 254G5RAc012809;\n Sat, 4 Jun 2022 09:32:13 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gg6wq0dsy-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Sat, 04 Jun 2022 09:32:13 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Sat, 4 Jun 2022 09:32:11 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 4 Jun 2022 09:32:11 -0700", "from localhost.localdomain (unknown [10.28.34.39])\n by maili.marvell.com (Postfix) with ESMTP id B80083F70AC;\n Sat, 4 Jun 2022 09:32:08 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=QBUci6xR4AyQZOXUhTsS/tPlTBJn48ZhvrLHFxSQnpg=;\n b=VBYJ6iwKtpoq+g0yyOL8zwBqO+OwoLkJ2nBYKY/gGXNeu9xE4JuE3TC1m+mpUWpkoE4H\n OB3U4NRwt8XyRxr513sSi+R0aynLh5MmPyzSUTbZ2C1stwMXHCRt9fNckcBmikmi8gXa\n xtDLrJXXkvS7VQIPQWbnif2xejEjX7C+cc04w2dXjbCJ7kaGhrbsMq5NRX1l3crExkWc\n JOLlvnazIzwwouJFDDJJ++yCQV+bG7X/pAT779H1ZF3aEpTv2/Ro621gdQ7FsK07xbed\n rtHUCbwnJo5p+ekYZScVNMv/zuCfqE3nCtHiGtd0JgSZgsiymsFq7/XF3wVRNnQQcCWk LA==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>,\n \"Shijith Thotton\" <sthotton@marvell.com>", "CC": "<thomas@monjalon.net>, <jerinj@marvell.com>, Tomasz Duszynski\n <tduszynski@marvell.com>", "Subject": "[PATCH] common/cnxk: allow building generic arm64 target for\n cn9k/cn10k", "Date": "Sat, 4 Jun 2022 18:31:57 +0200", "Message-ID": "<20220604163157.3509505-1-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "H4aEnzq51P558-AMVh7GXOb_8V5z0BT-", "X-Proofpoint-GUID": "H4aEnzq51P558-AMVh7GXOb_8V5z0BT-", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514\n definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Allow building generic arm64 target using config/arm/arm64_armv8_linux_*\nconfig which works on both cn9k and cn10k by relaxing cache line size\nrequirements a bit.\n\nWhile at it move cache line checks to common place.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nReviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>\n---\n drivers/common/cnxk/roc_dev.c | 26 ++++++++++++++++++++++++++\n drivers/event/cnxk/cn10k_eventdev.c | 5 -----\n drivers/event/cnxk/cn9k_eventdev.c | 5 -----\n drivers/net/cnxk/cn10k_ethdev.c | 5 -----\n drivers/net/cnxk/cn9k_ethdev.c | 5 -----\n 5 files changed, 26 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c\nindex 9a869698c4..09199ac2ff 100644\n--- a/drivers/common/cnxk/roc_dev.c\n+++ b/drivers/common/cnxk/roc_dev.c\n@@ -1094,6 +1094,29 @@ dev_lmt_setup(struct dev *dev)\n \treturn -errno;\n }\n \n+static bool\n+dev_cache_line_size_valid(void)\n+{\n+\tif (roc_model_is_cn9k()) {\n+\t\tif (PLT_CACHE_LINE_SIZE != 128) {\n+\t\t\tplt_err(\"Cache line size of %d is wrong for CN9K\",\n+\t\t\t\tPLT_CACHE_LINE_SIZE);\n+\t\t\treturn false;\n+\t\t}\n+\t} else if (roc_model_is_cn10k()) {\n+\t\tif (PLT_CACHE_LINE_SIZE == 128) {\n+\t\t\tplt_warn(\"Cache line size of %d might affect performance\",\n+\t\t\t\t PLT_CACHE_LINE_SIZE);\n+\t\t} else if (PLT_CACHE_LINE_SIZE != 64) {\n+\t\t\tplt_err(\"Cache line size of %d is wrong for CN10K\",\n+\t\t\t\tPLT_CACHE_LINE_SIZE);\n+\t\t\treturn false;\n+\t\t}\n+\t}\n+\n+\treturn true;\n+}\n+\n int\n dev_init(struct dev *dev, struct plt_pci_device *pci_dev)\n {\n@@ -1102,6 +1125,9 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)\n \tuintptr_t vf_mbase = 0;\n \tuint64_t intr_offset;\n \n+\tif (!dev_cache_line_size_valid())\n+\t\treturn -EFAULT;\n+\n \tbar2 = (uintptr_t)pci_dev->mem_resource[2].addr;\n \tbar4 = (uintptr_t)pci_dev->mem_resource[4].addr;\n \tif (bar2 == 0 || bar4 == 0) {\ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 77f0c28160..25d01fd90a 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -963,11 +963,6 @@ cn10k_sso_init(struct rte_eventdev *event_dev)\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tint rc;\n \n-\tif (RTE_CACHE_LINE_SIZE != 64) {\n-\t\tplt_err(\"Driver not compiled for CN10K\");\n-\t\treturn -EFAULT;\n-\t}\n-\n \trc = roc_plt_init();\n \tif (rc < 0) {\n \t\tplt_err(\"Failed to initialize platform model\");\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex 4d45f02c1c..6fef15e352 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -1193,11 +1193,6 @@ cn9k_sso_init(struct rte_eventdev *event_dev)\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tint rc;\n \n-\tif (RTE_CACHE_LINE_SIZE != 128) {\n-\t\tplt_err(\"Driver not compiled for CN9K\");\n-\t\treturn -EFAULT;\n-\t}\n-\n \trc = roc_plt_init();\n \tif (rc < 0) {\n \t\tplt_err(\"Failed to initialize platform model\");\ndiff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c\nindex 4cd82af7e5..33f61743f9 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.c\n+++ b/drivers/net/cnxk/cn10k_ethdev.c\n@@ -759,11 +759,6 @@ cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \tstruct cnxk_eth_dev *dev;\n \tint rc;\n \n-\tif (RTE_CACHE_LINE_SIZE != 64) {\n-\t\tplt_err(\"Driver not compiled for CN10K\");\n-\t\treturn -EFAULT;\n-\t}\n-\n \trc = roc_plt_init();\n \tif (rc) {\n \t\tplt_err(\"Failed to initialize platform model, rc=%d\", rc);\ndiff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c\nindex a388b3a8a6..fb34d20759 100644\n--- a/drivers/net/cnxk/cn9k_ethdev.c\n+++ b/drivers/net/cnxk/cn9k_ethdev.c\n@@ -689,11 +689,6 @@ cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \tstruct cnxk_eth_dev *dev;\n \tint rc;\n \n-\tif (RTE_CACHE_LINE_SIZE != 128) {\n-\t\tplt_err(\"Driver not compiled for CN9K\");\n-\t\treturn -EFAULT;\n-\t}\n-\n \trc = roc_plt_init();\n \tif (rc) {\n \t\tplt_err(\"Failed to initialize platform model, rc=%d\", rc);\n", "prefixes": [] }