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GET /api/patches/112302/?format=api
{ "id": 112302, "url": "http://patches.dpdk.org/api/patches/112302/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220603124821.1148119-2-spiked@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220603124821.1148119-2-spiked@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220603124821.1148119-2-spiked@nvidia.com", "date": "2022-06-03T12:48:15", "name": "[v4,1/7] net/mlx5: add LWM support for Rxq", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "25526add26c35ee5eb9c77ced2a320cef2d33d64", "submitter": { "id": 2637, "url": "http://patches.dpdk.org/api/people/2637/?format=api", "name": "Spike Du", "email": "spiked@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220603124821.1148119-2-spiked@nvidia.com/mbox/", "series": [ { "id": 23319, "url": "http://patches.dpdk.org/api/series/23319/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23319", "date": "2022-06-03T12:48:14", "name": "introduce per-queue fill threshold and host shaper", "version": 4, "mbox": "http://patches.dpdk.org/series/23319/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/112302/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/112302/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 80F80A0560;\n\tFri, 3 Jun 2022 14:48:54 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8E62B42B95;\n\tFri, 3 Jun 2022 14:48:49 +0200 (CEST)", "from NAM04-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam04on2045.outbound.protection.outlook.com [40.107.102.45])\n by mails.dpdk.org (Postfix) with ESMTP id E585F42B95\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Spike Du <spiked@nvidia.com>", "To": "<matan@nvidia.com>, <viacheslavo@nvidia.com>, <orika@nvidia.com>,\n <thomas@monjalon.net>, Shahaf Shuler <shahafs@nvidia.com>", "CC": "<andrew.rybchenko@oktetlabs.ru>, <stephen@networkplumber.org>,\n <mb@smartsharesystems.com>, <dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH v4 1/7] net/mlx5: add LWM support for Rxq", "Date": "Fri, 3 Jun 2022 15:48:15 +0300", "Message-ID": "<20220603124821.1148119-2-spiked@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20220603124821.1148119-1-spiked@nvidia.com>", "References": "<20220524152041.737154-1-spiked@nvidia.com>\n <20220603124821.1148119-1-spiked@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "5ebb2e75-05f6-4d09-24c4-08da455f6533", "X-MS-TrafficTypeDiagnostic": "BYAPR12MB3448:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BYAPR12MB34486894A859F091BFE0495DA8A19@BYAPR12MB3448.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n BRHzMrKd30nMvQBktDg1RwQKIIz6ni/pJuo0XyuBt+HP8uTPjrxJR3pR2idrYIbGE/Ri6oGsRECfVkHYHqreni+DXR7NXw8NEkbK6c9jRXvKaxmekM8NyKavfjh6lKcAwTzGWeS9CmI6u+1EmJaPdt/vkO5SA5sSpafm/tdnENwITh64ln9OfCZI0JjhTS8BFaloVzVJ+XiCknObipC0lD/rISbc4SaHmMo+4qkeSNAIOQg5APifc6geXsh9HsGQQwk2WKwJY/1xeiISEzAJ6kDFX/GxBjCYlvUTR7a1PFfKczuig6TvIGtTCpPeJn4FRberd+UN0mTQQkWHikEAwdV1SeClYBuix8X7CxcOOv7yJ4b5n5CwG+gP1sfEGusRaH0EXSy3uj3Afn4YIVROxmvG2+8quKsCmQmsXhLMVDg8VVYbO9Lb31Rl+VPizsXOL2X+bpKM78Pi93iItcmSL20NGJPb1xYLJmBLjZvV/C8AZG7yzUREew6jsJrSEYC8yGUQY/DVYJWvhaJz+4NgtgShqAPjrZ1BCgJDt1a536JkCSXrub4Nzdg0ZA09APBt4jIzkKiJrrU8+xfrs69jNlsRUFpxjNaxhVvd8Jf5AHilinGVelYI+mTXQpW1qwxUglpj24DKWtt02MtvKjXzHJeyrxIh8hpsuKqeACujF/s72TuY+PXujAGq32LAnW0c01OuKC3GUMMJahlKOFdY9g==", "X-Forefront-Antispam-Report": "CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(8676002)(36860700001)(7696005)(40460700003)(2906002)(54906003)(6636002)(6286002)(55016003)(83380400001)(36756003)(336012)(426003)(47076005)(82310400005)(316002)(110136005)(16526019)(70586007)(107886003)(81166007)(86362001)(70206006)(8936002)(2616005)(186003)(4326008)(356005)(5660300002)(1076003)(26005)(6666004)(508600001)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "03 Jun 2022 12:48:44.7313 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5ebb2e75-05f6-4d09-24c4-08da455f6533", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT019.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR12MB3448", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add lwm(Limit WaterMark) field to Rxq object which indicates the percentage\nof RX queue size used by HW to raise LWM event to the user.\nAllow LWM setting in modify_rq command.\nAllow the LWM configuration dynamically by adding RDY2RDY state change.\n\nSigned-off-by: Spike Du <spiked@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_devx.c | 13 ++++++++++++-\n drivers/net/mlx5/mlx5_devx.h | 1 +\n drivers/net/mlx5/mlx5_rx.h | 1 +\n 4 files changed, 15 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex ef755ee..305edff 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1395,6 +1395,7 @@ enum mlx5_rxq_modify_type {\n \tMLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */\n \tMLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */\n \tMLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */\n+\tMLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */\n };\n \n enum mlx5_txq_modify_type {\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 4b48f94..c918a50 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -62,7 +62,7 @@\n * @return\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static int\n+int\n mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type)\n {\n \tstruct mlx5_devx_modify_rq_attr rq_attr;\n@@ -76,6 +76,11 @@\n \tcase MLX5_RXQ_MOD_RST2RDY:\n \t\trq_attr.rq_state = MLX5_RQC_STATE_RST;\n \t\trq_attr.state = MLX5_RQC_STATE_RDY;\n+\t\tif (rxq->lwm) {\n+\t\t\trq_attr.modify_bitmask |=\n+\t\t\t\tMLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM;\n+\t\t\trq_attr.lwm = rxq->lwm;\n+\t\t}\n \t\tbreak;\n \tcase MLX5_RXQ_MOD_RDY2ERR:\n \t\trq_attr.rq_state = MLX5_RQC_STATE_RDY;\n@@ -85,6 +90,12 @@\n \t\trq_attr.rq_state = MLX5_RQC_STATE_RDY;\n \t\trq_attr.state = MLX5_RQC_STATE_RST;\n \t\tbreak;\n+\tcase MLX5_RXQ_MOD_RDY2RDY:\n+\t\trq_attr.rq_state = MLX5_RQC_STATE_RDY;\n+\t\trq_attr.state = MLX5_RQC_STATE_RDY;\n+\t\trq_attr.modify_bitmask |= MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM;\n+\t\trq_attr.lwm = rxq->lwm;\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_devx.h b/drivers/net/mlx5/mlx5_devx.h\nindex a95207a..ebd1da4 100644\n--- a/drivers/net/mlx5/mlx5_devx.h\n+++ b/drivers/net/mlx5/mlx5_devx.h\n@@ -11,6 +11,7 @@\n int mlx5_txq_devx_modify(struct mlx5_txq_obj *obj,\n \t\t\t enum mlx5_txq_modify_type type, uint8_t dev_port);\n void mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj);\n+int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type);\n \n extern struct mlx5_obj_ops devx_obj_ops;\n \ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex e715ed6..25a5f2c 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -175,6 +175,7 @@ struct mlx5_rxq_priv {\n \tstruct mlx5_devx_rq devx_rq;\n \tstruct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */\n \tuint32_t hairpin_status; /* Hairpin binding status. */\n+\tuint32_t lwm:16;\n };\n \n /* External RX queue descriptor. */\n", "prefixes": [ "v4", "1/7" ] }