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GET /api/patches/112132/?format=api
{ "id": 112132, "url": "http://patches.dpdk.org/api/patches/112132/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220531100245.542300-7-zhoumin@loongson.cn/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220531100245.542300-7-zhoumin@loongson.cn>", "list_archive_url": "https://inbox.dpdk.org/dev/20220531100245.542300-7-zhoumin@loongson.cn", "date": "2022-05-31T10:02:27", "name": "[v2,06/24] eal/loongarch: add cpu flag checks for LoongArch", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a455b3d1ccf4d55f235a13990f9e993ed27e7cbd", "submitter": { "id": 2394, "url": "http://patches.dpdk.org/api/people/2394/?format=api", "name": "zhoumin", "email": "zhoumin@loongson.cn" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220531100245.542300-7-zhoumin@loongson.cn/mbox/", "series": [ { "id": 23262, "url": "http://patches.dpdk.org/api/series/23262/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23262", "date": "2022-05-31T10:02:32", "name": "Support LoongArch architecture", "version": 2, "mbox": "http://patches.dpdk.org/series/23262/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/112132/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/112132/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5528FA0542;\n\tTue, 31 May 2022 12:04:38 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3E3DC42BA5;\n\tTue, 31 May 2022 12:03:30 +0200 (CEST)", "from loongson.cn (mail.loongson.cn [114.242.206.163])\n by mails.dpdk.org (Postfix) with ESMTP id 56C16427F3\n for <dev@dpdk.org>; Tue, 31 May 2022 12:03:12 +0200 (CEST)", "from localhost.localdomain (unknown [10.2.5.185])\n by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dx307F55Vi1qUJAA--.589S8;\n Tue, 31 May 2022 18:02:54 +0800 (CST)" ], "From": "Min Zhou <zhoumin@loongson.cn>", "To": "thomas@monjalon.net, david.marchand@redhat.com,\n bruce.richardson@intel.com,\n anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com,\n jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru", "Cc": "dev@dpdk.org,\n\tmaobibo@loongson.cn", "Subject": "[v2 06/24] eal/loongarch: add cpu flag checks for LoongArch", "Date": "Tue, 31 May 2022 18:02:27 +0800", "Message-Id": "<20220531100245.542300-7-zhoumin@loongson.cn>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220531100245.542300-1-zhoumin@loongson.cn>", "References": "<20220531100245.542300-1-zhoumin@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "AQAAf9Dx307F55Vi1qUJAA--.589S8", "X-Coremail-Antispam": "1UD129KBjvJXoWxAF4rur1kKryUCr47WFy5twb_yoWrWrWUpa\n yfCFy5Xw48Xr12k3yxXayjgF1rCF1xGF47AasxCw4Yva9rG34UZwsYkF93WF45A3yUXrnI\n gayY93y29FyUZw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU==", "X-CM-SenderInfo": "52kr3ztlq6z05rqj20fqof0/", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch uses aux vector software register to get CPU flags\nand add CPU flag checking support for LoongArch architecture.\n\nSigned-off-by: Min Zhou <zhoumin@loongson.cn>\n---\n lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++++\n lib/eal/loongarch/rte_cpuflags.c | 94 ++++++++++++++++++++++++\n 2 files changed, 133 insertions(+)\n create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h\n create mode 100644 lib/eal/loongarch/rte_cpuflags.c", "diff": "diff --git a/lib/eal/loongarch/include/rte_cpuflags.h b/lib/eal/loongarch/include/rte_cpuflags.h\nnew file mode 100644\nindex 0000000000..d9121a00a8\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_cpuflags.h\n@@ -0,0 +1,39 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef _RTE_CPUFLAGS_LOONGARCH_H_\n+#define _RTE_CPUFLAGS_LOONGARCH_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/**\n+ * Enumeration of all CPU features supported\n+ */\n+enum rte_cpu_flag_t {\n+\tRTE_CPUFLAG_CPUCFG = 0,\n+\tRTE_CPUFLAG_LAM,\n+\tRTE_CPUFLAG_UAL,\n+\tRTE_CPUFLAG_FPU,\n+\tRTE_CPUFLAG_LSX,\n+\tRTE_CPUFLAG_LASX,\n+\tRTE_CPUFLAG_CRC32,\n+\tRTE_CPUFLAG_COMPLEX,\n+\tRTE_CPUFLAG_CRYPTO,\n+\tRTE_CPUFLAG_LVZ,\n+\tRTE_CPUFLAG_LBT_X86,\n+\tRTE_CPUFLAG_LBT_ARM,\n+\tRTE_CPUFLAG_LBT_MIPS,\n+\t/* The last item */\n+\tRTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */\n+};\n+\n+#include \"generic/rte_cpuflags.h\"\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_CPUFLAGS_LOONGARCH_H_ */\ndiff --git a/lib/eal/loongarch/rte_cpuflags.c b/lib/eal/loongarch/rte_cpuflags.c\nnew file mode 100644\nindex 0000000000..4abcd0fdb3\n--- /dev/null\n+++ b/lib/eal/loongarch/rte_cpuflags.c\n@@ -0,0 +1,94 @@\n+/*\n+ * SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#include \"rte_cpuflags.h\"\n+\n+#include <elf.h>\n+#include <fcntl.h>\n+#include <assert.h>\n+#include <unistd.h>\n+#include <string.h>\n+\n+/* Symbolic values for the entries in the auxiliary table */\n+#define AT_HWCAP 16\n+#define AT_HWCAP2 26\n+\n+/* software based registers */\n+enum cpu_register_t {\n+\tREG_NONE = 0,\n+\tREG_HWCAP,\n+\tREG_MAX\n+};\n+\n+typedef uint32_t hwcap_registers_t[REG_MAX];\n+\n+struct feature_entry {\n+\tuint32_t reg;\n+\tuint32_t bit;\n+#define CPU_FLAG_NAME_MAX_LEN 64\n+\tchar name[CPU_FLAG_NAME_MAX_LEN];\n+};\n+\n+#define FEAT_DEF(name, reg, bit) \\\n+\t[RTE_CPUFLAG_##name] = {reg, bit, #name},\n+\n+const struct feature_entry rte_cpu_feature_table[] = {\n+\tFEAT_DEF(CPUCFG, REG_HWCAP, 0)\n+\tFEAT_DEF(LAM, REG_HWCAP, 1)\n+\tFEAT_DEF(UAL, REG_HWCAP, 2)\n+\tFEAT_DEF(FPU, REG_HWCAP, 3)\n+\tFEAT_DEF(LSX, REG_HWCAP, 4)\n+\tFEAT_DEF(LASX, REG_HWCAP, 5)\n+\tFEAT_DEF(CRC32, REG_HWCAP, 6)\n+\tFEAT_DEF(COMPLEX, REG_HWCAP, 7)\n+\tFEAT_DEF(CRYPTO, REG_HWCAP, 8)\n+\tFEAT_DEF(LVZ, REG_HWCAP, 9)\n+\tFEAT_DEF(LBT_X86, REG_HWCAP, 10)\n+\tFEAT_DEF(LBT_ARM, REG_HWCAP, 11)\n+\tFEAT_DEF(LBT_MIPS, REG_HWCAP, 12)\n+};\n+\n+/*\n+ * Read AUXV software register and get cpu features for LoongArch\n+ */\n+static void\n+rte_cpu_get_features(hwcap_registers_t out)\n+{\n+\tout[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);\n+}\n+\n+/*\n+ * Checks if a particular flag is available on current machine.\n+ */\n+int\n+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)\n+{\n+\tconst struct feature_entry *feat;\n+\thwcap_registers_t regs = {0};\n+\n+\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n+\t\treturn -ENOENT;\n+\n+\tfeat = &rte_cpu_feature_table[feature];\n+\tif (feat->reg == REG_NONE)\n+\t\treturn -EFAULT;\n+\n+\trte_cpu_get_features(regs);\n+\treturn (regs[feat->reg] >> feat->bit) & 1;\n+}\n+\n+const char *\n+rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)\n+{\n+\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n+\t\treturn NULL;\n+\treturn rte_cpu_feature_table[feature].name;\n+}\n+\n+void\n+rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)\n+{\n+\tmemset(intrinsics, 0, sizeof(*intrinsics));\n+}\n", "prefixes": [ "v2", "06/24" ] }