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{
    "id": 11187,
    "url": "http://patches.dpdk.org/api/patches/11187/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1457424877-26234-25-git-send-email-helin.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1457424877-26234-25-git-send-email-helin.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1457424877-26234-25-git-send-email-helin.zhang@intel.com",
    "date": "2016-03-08T08:14:32",
    "name": "[dpdk-dev,v5,24/29] i40e: expose some registers",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "039e4eb8cfde6b230502ff11c4af33da24e133cf",
    "submitter": {
        "id": 14,
        "url": "http://patches.dpdk.org/api/people/14/?format=api",
        "name": "Zhang, Helin",
        "email": "helin.zhang@intel.com"
    },
    "delegate": {
        "id": 10,
        "url": "http://patches.dpdk.org/api/users/10/?format=api",
        "username": "bruce",
        "first_name": "Bruce",
        "last_name": "Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1457424877-26234-25-git-send-email-helin.zhang@intel.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/11187/comments/",
    "check": "pending",
    "checks": "http://patches.dpdk.org/api/patches/11187/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 36ECF569E;\n\tTue,  8 Mar 2016 09:15:40 +0100 (CET)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 581A02C67\n\tfor <dev@dpdk.org>; Tue,  8 Mar 2016 09:15:38 +0100 (CET)",
            "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby orsmga102.jf.intel.com with ESMTP; 08 Mar 2016 00:15:38 -0800",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby FMSMGA003.fm.intel.com with ESMTP; 08 Mar 2016 00:15:36 -0800",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id u288FYtF009637;\n\tTue, 8 Mar 2016 16:15:34 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid u288FUWv027136; Tue, 8 Mar 2016 16:15:32 +0800",
            "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u288FUan027132; \n\tTue, 8 Mar 2016 16:15:30 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.22,556,1449561600\"; d=\"scan'208\";a=\"665665853\"",
        "From": "Helin Zhang <helin.zhang@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Tue,  8 Mar 2016 16:14:32 +0800",
        "Message-Id": "<1457424877-26234-25-git-send-email-helin.zhang@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "In-Reply-To": "<1457424877-26234-1-git-send-email-helin.zhang@intel.com>",
        "References": "<1457278919-30800-1-git-send-email-helin.zhang@intel.com>\n\t<1457424877-26234-1-git-send-email-helin.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v5 24/29] i40e: expose some registers",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch adds 7 new register definitions for programming the\nparser, flow director and RSS blocks in the HW.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nAcked-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n drivers/net/i40e/base/i40e_register.h | 48 +++++++++++++++++++++++++++++++++++\n drivers/net/i40e/i40e_ethdev.c        | 11 ++------\n 2 files changed, 50 insertions(+), 9 deletions(-)\n\nv4:\n - Reworded the commit logs.",
    "diff": "diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h\nindex 6e56620..fd0a723 100644\n--- a/drivers/net/i40e/base/i40e_register.h\n+++ b/drivers/net/i40e/base/i40e_register.h\n@@ -2056,6 +2056,14 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_PRTPM_TLPIC              0x001E43C0 /* Reset: GLOBR */\n #define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0\n #define I40E_PRTPM_TLPIC_ETLPIC_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)\n+#define I40E_GL_PRS_FVBM(_i)                 (0x00269760 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */\n+#define I40E_GL_PRS_FVBM_MAX_INDEX           3\n+#define I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT  0\n+#define I40E_GL_PRS_FVBM_FV_BYTE_INDX_MASK   I40E_MASK(0x7F, I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT)\n+#define I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT 8\n+#define I40E_GL_PRS_FVBM_RULE_BUS_INDX_MASK  I40E_MASK(0x3F, I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT)\n+#define I40E_GL_PRS_FVBM_MSK_ENA_SHIFT       31\n+#define I40E_GL_PRS_FVBM_MSK_ENA_MASK        I40E_MASK(0x1, I40E_GL_PRS_FVBM_MSK_ENA_SHIFT)\n #define I40E_GLRPB_DPSS               0x000AC828 /* Reset: CORER */\n #define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0\n #define I40E_GLRPB_DPSS_DPS_TCN_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT)\n@@ -2227,6 +2235,14 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_PRTQF_FD_FLXINSET_MAX_INDEX   63\n #define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0\n #define I40E_PRTQF_FD_FLXINSET_INSET_MASK  I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT)\n+#define I40E_PRTQF_FD_INSET(_i, _j)      (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */\n+#define I40E_PRTQF_FD_INSET_MAX_INDEX   63\n+#define I40E_PRTQF_FD_INSET_INSET_SHIFT 0\n+#define I40E_PRTQF_FD_INSET_INSET_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT)\n+#define I40E_PRTQF_FD_INSET(_i, _j)      (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */\n+#define I40E_PRTQF_FD_INSET_MAX_INDEX   63\n+#define I40E_PRTQF_FD_INSET_INSET_SHIFT 0\n+#define I40E_PRTQF_FD_INSET_INSET_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT)\n #define I40E_PRTQF_FD_MSK(_i, _j)       (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */\n #define I40E_PRTQF_FD_MSK_MAX_INDEX    63\n #define I40E_PRTQF_FD_MSK_MASK_SHIFT   0\n@@ -5169,6 +5185,38 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_GLQF_FD_PCTYPES_MAX_INDEX       63\n #define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT 0\n #define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_MASK  I40E_MASK(0x3F, I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT)\n+#define I40E_GLQF_FD_MSK(_i, _j)       (0x00267200 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */\n+#define I40E_GLQF_FD_MSK_MAX_INDEX    1\n+#define I40E_GLQF_FD_MSK_MASK_SHIFT   0\n+#define I40E_GLQF_FD_MSK_MASK_MASK    I40E_MASK(0xFFFF, I40E_GLQF_FD_MSK_MASK_SHIFT)\n+#define I40E_GLQF_FD_MSK_OFFSET_SHIFT 16\n+#define I40E_GLQF_FD_MSK_OFFSET_MASK  I40E_MASK(0x3F, I40E_GLQF_FD_MSK_OFFSET_SHIFT)\n+#define I40E_GLQF_HASH_INSET(_i, _j)      (0x00267600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */\n+#define I40E_GLQF_HASH_INSET_MAX_INDEX   1\n+#define I40E_GLQF_HASH_INSET_INSET_SHIFT 0\n+#define I40E_GLQF_HASH_INSET_INSET_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_HASH_INSET_INSET_SHIFT)\n+#define I40E_GLQF_HASH_MSK(_i, _j)       (0x00267A00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */\n+#define I40E_GLQF_HASH_MSK_MAX_INDEX    1\n+#define I40E_GLQF_HASH_MSK_MASK_SHIFT   0\n+#define I40E_GLQF_HASH_MSK_MASK_MASK    I40E_MASK(0xFFFF, I40E_GLQF_HASH_MSK_MASK_SHIFT)\n+#define I40E_GLQF_HASH_MSK_OFFSET_SHIFT 16\n+#define I40E_GLQF_HASH_MSK_OFFSET_MASK  I40E_MASK(0x3F, I40E_GLQF_HASH_MSK_OFFSET_SHIFT)\n+#define I40E_GLQF_ORT(_i)               (0x00268900 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */\n+#define I40E_GLQF_ORT_MAX_INDEX         63\n+#define I40E_GLQF_ORT_PIT_INDX_SHIFT    0\n+#define I40E_GLQF_ORT_PIT_INDX_MASK     I40E_MASK(0x1F, I40E_GLQF_ORT_PIT_INDX_SHIFT)\n+#define I40E_GLQF_ORT_FIELD_CNT_SHIFT   5\n+#define I40E_GLQF_ORT_FIELD_CNT_MASK    I40E_MASK(0x3, I40E_GLQF_ORT_FIELD_CNT_SHIFT)\n+#define I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT 7\n+#define I40E_GLQF_ORT_FLX_PAYLOAD_MASK  I40E_MASK(0x1, I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT)\n+#define I40E_GLQF_PIT(_i)              (0x00268C80 + ((_i) * 4)) /* _i=0...23 */ /* Reset: CORER */\n+#define I40E_GLQF_PIT_MAX_INDEX        23\n+#define I40E_GLQF_PIT_SOURCE_OFF_SHIFT 0\n+#define I40E_GLQF_PIT_SOURCE_OFF_MASK  I40E_MASK(0x1F, I40E_GLQF_PIT_SOURCE_OFF_SHIFT)\n+#define I40E_GLQF_PIT_FSIZE_SHIFT      5\n+#define I40E_GLQF_PIT_FSIZE_MASK       I40E_MASK(0x1F, I40E_GLQF_PIT_FSIZE_SHIFT)\n+#define I40E_GLQF_PIT_DEST_OFF_SHIFT   10\n+#define I40E_GLQF_PIT_DEST_OFF_MASK    I40E_MASK(0x3F, I40E_GLQF_PIT_DEST_OFF_SHIFT)\n #define I40E_GLQF_FDEVICTENA(_i)                   (0x00270384 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */\n #define I40E_GLQF_FDEVICTENA_MAX_INDEX             1\n #define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT 0\ndiff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 82cc63a..088e8ba 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -137,13 +137,6 @@\n #define I40E_DEFAULT_DCB_APP_NUM    1\n #define I40E_DEFAULT_DCB_APP_PRIO   3\n \n-#define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))\n-#define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))\n-#define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF\n-#define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))\n-#define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))\n-#define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF\n-\n #define I40E_INSET_NONE            0x00000000000000000ULL\n \n /* bit0 ~ bit 7 */\n@@ -6973,7 +6966,7 @@ i40e_set_hash_inset_mask(struct i40e_hw *hw,\n \t\tfor (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {\n \t\t\treg = i40e_read_rx_ctl(hw,\n \t\t\t\t\t       I40E_GLQF_HASH_MSK(i, pctype));\n-\t\t\tif (reg & I40E_GLQF_HASH_MSK_FIELD)\n+\t\t\tif (reg & I40E_GLQF_HASH_MSK_MASK_MASK)\n \t\t\t\tcount++;\n \t\t}\n \t\tif (count + num > I40E_INSET_MASK_NUM_REG)\n@@ -7015,7 +7008,7 @@ i40e_set_fd_inset_mask(struct i40e_hw *hw,\n \t\tfor (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {\n \t\t\treg = i40e_read_rx_ctl(hw,\n \t\t\t\t\t       I40E_GLQF_FD_MSK(i, pctype));\n-\t\t\tif (reg & I40E_GLQF_FD_MSK_FIELD)\n+\t\t\tif (reg & I40E_GLQF_FD_MSK_MASK_MASK)\n \t\t\t\tcount++;\n \t\t}\n \t\tif (count + num > I40E_INSET_MASK_NUM_REG)\n",
    "prefixes": [
        "dpdk-dev",
        "v5",
        "24/29"
    ]
}