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GET /api/patches/111571/?format=api
{ "id": 111571, "url": "http://patches.dpdk.org/api/patches/111571/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220522055900.417282-2-spiked@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220522055900.417282-2-spiked@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220522055900.417282-2-spiked@nvidia.com", "date": "2022-05-22T05:58:54", "name": "[RFC,v2,1/7] net/mlx5: add LWM support for Rxq", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "25526add26c35ee5eb9c77ced2a320cef2d33d64", "submitter": { "id": 2637, "url": "http://patches.dpdk.org/api/people/2637/?format=api", "name": "Spike Du", "email": "spiked@nvidia.com" }, "delegate": { "id": 3961, "url": "http://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220522055900.417282-2-spiked@nvidia.com/mbox/", "series": [ { "id": 23078, "url": "http://patches.dpdk.org/api/series/23078/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23078", "date": "2022-05-22T05:58:53", "name": "introduce per-queue limit watermark and host shaper", "version": 2, "mbox": "http://patches.dpdk.org/series/23078/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/111571/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/111571/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=rvlg0A8LiXFB2eV6vnTAVEjy3SpW4k3Rp7QU7LqW24OmDeUcP/DAWHITHIIcqA25v47Jo0UH5y40lf34+LVg3SJi3BqxusAlgz1atKroPCMPLZrNSVx28eyLmJyDRE2wXQjeR86qNpkBm170YPQuYgHFLBsIkWeCeql9gSdN8dwyI1Xxwqj/z/xhOvxVJ6dtb0tx/6uo9A4fC7qXLfA9qSIOL3B/nzZWDMM8vn6ZOt7Ze14cxcrNDIuBvG/807T9paUbac7Xf6XdKwN2XLBFyCxJaEdYqaeNI5sVPjYct4vQPVVJXaw3LJTzlRnXP6JTy7yyhLUS7nQKCuIYdFQhug==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 12.22.5.236)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 12.22.5.236 as permitted sender) receiver=protection.outlook.com;\n client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C", "From": "Spike Du <spiked@nvidia.com>", "To": "<matan@nvidia.com>, <viacheslavo@nvidia.com>, <orika@nvidia.com>,\n <thomas@monjalon.net>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[RFC v2 1/7] net/mlx5: add LWM support for Rxq", "Date": "Sun, 22 May 2022 08:58:54 +0300", "Message-ID": "<20220522055900.417282-2-spiked@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20220522055900.417282-1-spiked@nvidia.com>", "References": "<20220506035645.4101714-1-spiked@nvidia.com>\n <20220522055900.417282-1-spiked@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "8b931eca-edca-48e6-5ccb-08da3bb83969", "X-MS-TrafficTypeDiagnostic": "BN9PR12MB5035:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BN9PR12MB5035C249248A24586CA3AB02A8D59@BN9PR12MB5035.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n +YsThRUWp0pD1V0BGm/GbAs4YemwGH+31H/a6yD/e2296koBqqjZKTsb0uj1wgBio7VtSMmj2OWECQpQ75JQjfLan4LP6qFbGE/BlB59xU0+SlmmIcD875bMnUp7aYo5gbd+6NatWASrz7YzZvoDlDB6HHYdgCNMqOF7/G1E9AeZ2ZqQSCs+YCHWSw92wArfNL1xts9y7QmwF3PCWXydfygJ0Z305CSeMR1TuD1b0LMISi2Ulhx4T7etPh6rXF9hssLsOCInEuzeqKZS8CfioE6HmaodbgtP6vwu7VYiHi4CIL9andGU1gyb/jmn6NaHUONsu9d48ncuyxzAlRHSUIsTZ7I+1jssbhmIWzDOhttfRLXEAisYkSamzTBJFg8JF2/9BXqq7PxaOINs9tpRxrNrgYwWcAOe9Wew1QaYw2JPVM7sWHWl/uU7fkMx/Mh68YXrvKGgvXxnz/j3UAsAcvTdzsd5eWabW2D+H7krrtQzUjFc65pkmq/gOhbVRITeX/4zwDLJJXCuGgFTPczjAfyYy/USrQvy1okLezvdQkyxL/cRiSDY18YFk7sxjfRcUcIgkZWTLrsLwf/GZoGrqLXZWCgOHcf1mlcKicdJI4uf1Keu+4UuT9EnueHv8vgaRNvwk2kFGlKVq/F5MajB/G5++yVZTfxzNPn+tlIwjY+CTHxEojtyn11nFqk1D62aREWB4Z3ddV2N1mIsum3xGQ==", "X-Forefront-Antispam-Report": "CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(54906003)(16526019)(8936002)(70206006)(426003)(186003)(47076005)(81166007)(70586007)(8676002)(4326008)(2616005)(336012)(1076003)(508600001)(55016003)(83380400001)(107886003)(110136005)(356005)(316002)(82310400005)(36756003)(6666004)(7696005)(40460700003)(36860700001)(86362001)(5660300002)(26005)(6286002)(2906002)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 May 2022 05:59:24.8324 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8b931eca-edca-48e6-5ccb-08da3bb83969", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT053.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN9PR12MB5035", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add lwm(Limit WaterMark) field to Rxq object which indicates the percentage\nof RX queue size used by HW to raise LWM event to the user.\nAllow LWM setting in modify_rq command.\nAllow the LWM configuration dynamically by adding RDY2RDY state change.\n\nSigned-off-by: Spike Du <spiked@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_devx.c | 13 ++++++++++++-\n drivers/net/mlx5/mlx5_devx.h | 1 +\n drivers/net/mlx5/mlx5_rx.h | 1 +\n 4 files changed, 15 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex ef755ee8cf..305edffe71 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1395,6 +1395,7 @@ enum mlx5_rxq_modify_type {\n \tMLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */\n \tMLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */\n \tMLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */\n+\tMLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */\n };\n \n enum mlx5_txq_modify_type {\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 4b48f9433a..c918a50ae9 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -62,7 +62,7 @@ mlx5_rxq_obj_modify_rq_vlan_strip(struct mlx5_rxq_priv *rxq, int on)\n * @return\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n-static int\n+int\n mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type)\n {\n \tstruct mlx5_devx_modify_rq_attr rq_attr;\n@@ -76,6 +76,11 @@ mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type)\n \tcase MLX5_RXQ_MOD_RST2RDY:\n \t\trq_attr.rq_state = MLX5_RQC_STATE_RST;\n \t\trq_attr.state = MLX5_RQC_STATE_RDY;\n+\t\tif (rxq->lwm) {\n+\t\t\trq_attr.modify_bitmask |=\n+\t\t\t\tMLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM;\n+\t\t\trq_attr.lwm = rxq->lwm;\n+\t\t}\n \t\tbreak;\n \tcase MLX5_RXQ_MOD_RDY2ERR:\n \t\trq_attr.rq_state = MLX5_RQC_STATE_RDY;\n@@ -85,6 +90,12 @@ mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type)\n \t\trq_attr.rq_state = MLX5_RQC_STATE_RDY;\n \t\trq_attr.state = MLX5_RQC_STATE_RST;\n \t\tbreak;\n+\tcase MLX5_RXQ_MOD_RDY2RDY:\n+\t\trq_attr.rq_state = MLX5_RQC_STATE_RDY;\n+\t\trq_attr.state = MLX5_RQC_STATE_RDY;\n+\t\trq_attr.modify_bitmask |= MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM;\n+\t\trq_attr.lwm = rxq->lwm;\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_devx.h b/drivers/net/mlx5/mlx5_devx.h\nindex a95207a6b9..ebd1da455a 100644\n--- a/drivers/net/mlx5/mlx5_devx.h\n+++ b/drivers/net/mlx5/mlx5_devx.h\n@@ -11,6 +11,7 @@ int mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx);\n int mlx5_txq_devx_modify(struct mlx5_txq_obj *obj,\n \t\t\t enum mlx5_txq_modify_type type, uint8_t dev_port);\n void mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj);\n+int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type);\n \n extern struct mlx5_obj_ops devx_obj_ops;\n \ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex e715ed6b62..25a5f2c1fa 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -175,6 +175,7 @@ struct mlx5_rxq_priv {\n \tstruct mlx5_devx_rq devx_rq;\n \tstruct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */\n \tuint32_t hairpin_status; /* Hairpin binding status. */\n+\tuint32_t lwm:16;\n };\n \n /* External RX queue descriptor. */\n", "prefixes": [ "RFC", "v2", "1/7" ] }