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GET /api/patches/110739/?format=api
{ "id": 110739, "url": "http://patches.dpdk.org/api/patches/110739/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220505173003.3242618-1-kda@semihalf.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220505173003.3242618-1-kda@semihalf.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220505173003.3242618-1-kda@semihalf.com", "date": "2022-05-05T17:29:52", "name": "[00/11] Introduce support for RISC-V architecture", "commit_ref": null, "pull_url": null, "state": null, "archived": false, "hash": null, "submitter": { "id": 2179, "url": "http://patches.dpdk.org/api/people/2179/?format=api", "name": "Stanislaw Kardach", "email": "kda@semihalf.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220505173003.3242618-1-kda@semihalf.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/110739/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/110739/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 87A39A00C2;\n\tThu, 5 May 2022 19:30:27 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4844140C35;\n\tThu, 5 May 2022 19:30:27 +0200 (CEST)", "from mail-lf1-f51.google.com (mail-lf1-f51.google.com\n [209.85.167.51]) by mails.dpdk.org (Postfix) with ESMTP id 4B06F40042\n for <dev@dpdk.org>; Thu, 5 May 2022 19:30:26 +0200 (CEST)", "by mail-lf1-f51.google.com with SMTP id w1so8627905lfa.4\n for <dev@dpdk.org>; Thu, 05 May 2022 10:30:26 -0700 (PDT)", "from localhost.localdomain (89-73-146-138.dynamic.chello.pl.\n [89.73.146.138]) by smtp.gmail.com with ESMTPSA id\n z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.24\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 05 May 2022 10:30:25 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=semihalf-com.20210112.gappssmtp.com; s=20210112;\n h=from:to:cc:subject:date:message-id:mime-version\n :content-transfer-encoding;\n bh=HVW8rhq/wffOU8TJUuP+/b0JTSkDx9przzbPmdY+C4M=;\n b=hmdqSEvX35gPpBLR2z1Rb9M3jxG/H9uc4HIJ1YQs722zBBg4MZgi3RPgP19geBwa2t\n qjJGl+UwrJAA+k0LxtEh93Nw9tig3+kmOQwWC32Pmgb6B+0ZimnnCRbBl9DerYnG4i2Z\n K/pIHcVdQmxTr6tdRyuMGPoSUM+aaynzPZxkD0DaZ46wMu9n/SxAZr0d0ZFbslOckwSN\n SA6LTEjjOXWEfn9G05Cl3bpuX1oFhq5WnXps0xjIN0Kb3ckI/jF9tRSQkV85RYAF5eyf\n HLkr9QhG56IO+vmy++pVnwm90ntFb6z/BOcCULylBj+L0uw1CzqsnKb9gLxRc8htL4Vc\n F+Sg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20210112;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version\n :content-transfer-encoding;\n bh=HVW8rhq/wffOU8TJUuP+/b0JTSkDx9przzbPmdY+C4M=;\n b=IV6mHtkaIkc8PWU2DWlwoi35vO7ELR7ryCtRGwz2k5msV2BOdTHjACEVVVNoCKrYmM\n aEM1IbwJX/7HmITtSCJrVm3xKT0DCA958yI1aempqRZxoVT1Z6neXiPYh0jXITHYlzVl\n 2jCtr/kXthk0iy0CXLA4q0Cr8CCdPS0PualSCh7nxQoqBc+r1vHrv0xzHSA/0pvyQsX4\n MPVxPfdwkUoUclzL9V3tlol3YkU7LI/I5y2eN9cxv/S5h2kHZVVnYPkXLjSN0VoGZGet\n yjLZxETiAkdtfyqNBYzE3m5xSLGjEVKJVEOiUSP2+ph4OfQd9U5PLl8EfBu7r7UmHCTr\n fYqA==", "X-Gm-Message-State": "AOAM532gn1oYZSVIr4fBZcHW9N8Jj+NzFeE7c+gWLr27jtL9wwa9r3s6\n VYHhWTLP+fGhRwfapqY24WU/9sseHlPJSA==", "X-Google-Smtp-Source": "\n ABdhPJw640b/uuXbiodJrLG9RrIbZ36N9vIuZxzGUqoEEr+itjEwJsKRihdWl/MsswTkJQkv49NQ6g==", "X-Received": "by 2002:ac2:57c7:0:b0:472:208d:926f with SMTP id\n k7-20020ac257c7000000b00472208d926fmr18095103lfo.224.1651771825690;\n Thu, 05 May 2022 10:30:25 -0700 (PDT)", "From": "Stanislaw Kardach <kda@semihalf.com>", "To": "dev@dpdk.org", "Cc": "Stanislaw Kardach <kda@semihalf.com>,\n Frank Zhao <Frank.Zhao@starfivetech.com>, Sam Grove <sam.grove@sifive.com>,\n mw@semihalf.com, upstream@semihalf.com", "Subject": "[PATCH 00/11] Introduce support for RISC-V architecture", "Date": "Thu, 5 May 2022 19:29:52 +0200", "Message-Id": "<20220505173003.3242618-1-kda@semihalf.com>", "X-Mailer": "git-send-email 2.30.2", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patchset adds support for building and running DPDK on 64bit RISC-V\narchitecture. The initial support targets rv64gc (rv64imafdc) ISA and\nwas tested on SiFive Unmatched development board with the Freedom U740\nSoC running Linux (freedom-u-sdk based kernel).\nI have tested this codebase using DPDK unit and perf tests as well as\ntest-pmd, l2fwd and l3fwd examples.\nThe NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD.\nOn the UIO side, since U740 does not have an IOMMU, I've used igb_uio,\nuio_pci_generic and vfio-pci noiommu drivers.\n\nCommits 1-2 fix small issues which are encountered if a given platform\n does not support any vector operations (which is the case with U740).\nCommit 3 introduces EAL and build system support for RISC-V architecture\n as well as documentation updates.\nCommits 4-7 add missing defines and stubs to enable RISC-V operation in\n non-EAL parts.\nCommit 8 adds RISC-V specific cpuflags test.\nCommit 9 works around a bug in the current GCC in test_ring compiled\n with -O0 or -Og.\nCommit 10 adds RISC-V testing to test-meson-builds.sh automatically\n iterating over cross-compile config files (currently present for\n generic rv64gc and SiFive U740).\nCommit 11 extends hash r/w perf test by displaying both HTM and non-HTM\n measurements. This is an extraneous commit which is not directly\n needed for RISC-V support but was noticed when we have started\n gathering test results. If needed, I can submit it separately.\n\nI appreciate Your comments and feedback.\n\nBest Regards,\nStanislaw Kardach\n\nNOTE: This work was sponsored by StarFive and SiFive which is signified by\n \"Sponsored-by:\" sign-offs in each commit message. After discussing it\n with Thomas Monjalon it seemed a better choice than \"Suggested-by\" which\n does not fully convey the nature of involvement. However it makes\n Linux checkpatch unhappy so I'm not sure if I shouldn't change the\n sign-offs.\n\nNOTE2: I have added maintainers for each commit based on MAINTAINERS file.\n However some modules (l3fwd, net/tap and cpuflags unit tests) do not have\n any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as\n if it was a commit adding new files.\n\nMichal Mazurek (3):\n lpm: add a scalar version of lookupx4 function\n eal: add initial support for RISC-V architecture\n test/cpuflags: add test for RISC-V cpu flag\n\nStanislaw Kardach (8):\n examples/l3fwd: fix scalar LPM compilation\n net/ixgbe: enable vector stubs for RISC-V\n net/memif: set memfd syscall ID on RISC-V\n net/tap: set BPF syscall ID for RISC-V\n examples/l3fwd: enable RISC-V operation\n test/ring: disable problematic tests for RISC-V\n devtools: add RISC-V to test-meson-builds.sh\n test/hash: report non HTM numbers for single r/w\n\n MAINTAINERS | 6 +\n app/test/test_cpuflags.c | 81 ++++++++++\n app/test/test_hash_readwrite.c | 8 +-\n app/test/test_ring.c | 8 +\n app/test/test_xmmt_ops.h | 16 ++\n config/meson.build | 2 +\n config/riscv/meson.build | 148 ++++++++++++++++++\n config/riscv/riscv64_linux_gcc | 17 ++\n config/riscv/riscv64_sifive_u740_linux_gcc | 19 +++\n devtools/test-meson-builds.sh | 6 +\n doc/guides/contributing/design.rst | 2 +-\n .../linux_gsg/cross_build_dpdk_for_riscv.rst | 125 +++++++++++++++\n doc/guides/linux_gsg/index.rst | 1 +\n doc/guides/nics/features.rst | 5 +\n doc/guides/nics/features/default.ini | 1 +\n doc/guides/nics/features/ixgbe.ini | 1 +\n doc/guides/rel_notes/release_22_07.rst | 29 ++++\n drivers/net/i40e/meson.build | 6 +\n drivers/net/ixgbe/ixgbe_rxtx.c | 4 +-\n drivers/net/memif/rte_eth_memif.h | 2 +\n drivers/net/tap/tap_bpf.h | 2 +\n examples/l3fwd/l3fwd_em.c | 8 +\n examples/l3fwd/l3fwd_fib.c | 2 +\n examples/l3fwd/l3fwd_lpm.c | 2 +-\n lib/eal/riscv/include/meson.build | 23 +++\n lib/eal/riscv/include/rte_atomic.h | 52 ++++++\n lib/eal/riscv/include/rte_byteorder.h | 44 ++++++\n lib/eal/riscv/include/rte_cpuflags.h | 55 +++++++\n lib/eal/riscv/include/rte_cycles.h | 103 ++++++++++++\n lib/eal/riscv/include/rte_io.h | 21 +++\n lib/eal/riscv/include/rte_mcslock.h | 18 +++\n lib/eal/riscv/include/rte_memcpy.h | 63 ++++++++\n lib/eal/riscv/include/rte_pause.h | 31 ++++\n lib/eal/riscv/include/rte_pflock.h | 17 ++\n lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++\n lib/eal/riscv/include/rte_prefetch.h | 50 ++++++\n lib/eal/riscv/include/rte_rwlock.h | 44 ++++++\n lib/eal/riscv/include/rte_spinlock.h | 67 ++++++++\n lib/eal/riscv/include/rte_ticketlock.h | 21 +++\n lib/eal/riscv/include/rte_vect.h | 55 +++++++\n lib/eal/riscv/meson.build | 11 ++\n lib/eal/riscv/rte_cpuflags.c | 122 +++++++++++++++\n lib/eal/riscv/rte_cycles.c | 77 +++++++++\n lib/eal/riscv/rte_hypervisor.c | 13 ++\n lib/eal/riscv/rte_power_intrinsics.c | 56 +++++++\n lib/lpm/meson.build | 1 +\n lib/lpm/rte_lpm.h | 4 +-\n lib/lpm/rte_lpm_scalar.h | 122 +++++++++++++++\n meson.build | 2 +\n 49 files changed, 1588 insertions(+), 7 deletions(-)\n create mode 100644 config/riscv/meson.build\n create mode 100644 config/riscv/riscv64_linux_gcc\n create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc\n create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst\n create mode 100644 lib/eal/riscv/include/meson.build\n create mode 100644 lib/eal/riscv/include/rte_atomic.h\n create mode 100644 lib/eal/riscv/include/rte_byteorder.h\n create mode 100644 lib/eal/riscv/include/rte_cpuflags.h\n create mode 100644 lib/eal/riscv/include/rte_cycles.h\n create mode 100644 lib/eal/riscv/include/rte_io.h\n create mode 100644 lib/eal/riscv/include/rte_mcslock.h\n create mode 100644 lib/eal/riscv/include/rte_memcpy.h\n create mode 100644 lib/eal/riscv/include/rte_pause.h\n create mode 100644 lib/eal/riscv/include/rte_pflock.h\n create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h\n create mode 100644 lib/eal/riscv/include/rte_prefetch.h\n create mode 100644 lib/eal/riscv/include/rte_rwlock.h\n create mode 100644 lib/eal/riscv/include/rte_spinlock.h\n create mode 100644 lib/eal/riscv/include/rte_ticketlock.h\n create mode 100644 lib/eal/riscv/include/rte_vect.h\n create mode 100644 lib/eal/riscv/meson.build\n create mode 100644 lib/eal/riscv/rte_cpuflags.c\n create mode 100644 lib/eal/riscv/rte_cycles.c\n create mode 100644 lib/eal/riscv/rte_hypervisor.c\n create mode 100644 lib/eal/riscv/rte_power_intrinsics.c\n create mode 100644 lib/lpm/rte_lpm_scalar.h", "diff": null, "prefixes": [ "00/11" ] }