get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/110401/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 110401,
    "url": "http://patches.dpdk.org/api/patches/110401/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220428033034.3490183-3-wenjun1.wu@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220428033034.3490183-3-wenjun1.wu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220428033034.3490183-3-wenjun1.wu@intel.com",
    "date": "2022-04-28T03:30:27",
    "name": "[v9,2/9] net/ice/base: support queue BW allocation configuration",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "4e930c65c92632f26fbf396f1b3404d65e27150d",
    "submitter": {
        "id": 2083,
        "url": "http://patches.dpdk.org/api/people/2083/?format=api",
        "name": "Wenjun Wu",
        "email": "wenjun1.wu@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220428033034.3490183-3-wenjun1.wu@intel.com/mbox/",
    "series": [
        {
            "id": 22704,
            "url": "http://patches.dpdk.org/api/series/22704/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22704",
            "date": "2022-04-28T03:30:28",
            "name": "Enable ETS-based TX QoS on PF",
            "version": 9,
            "mbox": "http://patches.dpdk.org/series/22704/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/110401/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/110401/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 59EB3A0503;\n\tThu, 28 Apr 2022 05:53:02 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 131394068F;\n\tThu, 28 Apr 2022 05:52:53 +0200 (CEST)",
            "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 1D87C40691\n for <dev@dpdk.org>; Thu, 28 Apr 2022 05:52:50 +0200 (CEST)",
            "from orsmga003.jf.intel.com ([10.7.209.27])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 Apr 2022 20:52:43 -0700",
            "from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181])\n by orsmga003.jf.intel.com with ESMTP; 27 Apr 2022 20:52:42 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1651117971; x=1682653971;\n h=from:to:subject:date:message-id:in-reply-to:references:\n mime-version:content-transfer-encoding;\n bh=BCeKKmCoeiqtM9BOGYhY7vGXbguWchhw2/6bSnaD6pk=;\n b=Dj6A/eVSNvt5lSPTcR/TGO/tOg7Q3/XaPpYZfwf929lF6/qsgKcUr8qN\n f209m5KTPv5l3Vx3jYHwUaYrqPxwvj+Cnyhr98KEXsT+ZAtN4Xlpv6tgL\n oYPjeQv0QuqmleNmunPdPHFmcsUWnoO4uyvyKQtjfjfPC0xWhHnMv91ic\n 9GGq7kAGB9hut/JR4POyHxif4zE84StsoPdoer8vq2knFCB9hbL1gK8vU\n WxHs4+jqVj11tbwk+RGk3oXd4c7ju5Vzxx+YbMuiOV0J8eqs1N0PBbbih\n D6uMCvPk3uOzek/Whcc5EnJUuEuUKDiNBm2uhjM+FqCSXc1V0tnP4FSmw w==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6400,9594,10330\"; a=\"253531277\"",
            "E=Sophos;i=\"5.90,295,1643702400\"; d=\"scan'208\";a=\"253531277\"",
            "E=Sophos;i=\"5.90,295,1643702400\"; d=\"scan'208\";a=\"514044787\""
        ],
        "X-ExtLoop1": "1",
        "From": "Wenjun Wu <wenjun1.wu@intel.com>",
        "To": "dev@dpdk.org,\n\tqiming.yang@intel.com,\n\tqi.z.zhang@intel.com",
        "Subject": "[PATCH v9 2/9] net/ice/base: support queue BW allocation\n configuration",
        "Date": "Thu, 28 Apr 2022 11:30:27 +0800",
        "Message-Id": "<20220428033034.3490183-3-wenjun1.wu@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20220428033034.3490183-1-wenjun1.wu@intel.com>",
        "References": "<20220329014813.1092054-1-wenjun1.wu@intel.com>\n <20220428033034.3490183-1-wenjun1.wu@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "This patch adds BW allocation support of queue scheduling node\nto support WFQ in queue level.\n\nSigned-off-by: Wenjun Wu <wenjun1.wu@intel.com>\n---\n drivers/net/ice/base/ice_sched.c | 64 ++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_sched.h |  3 ++\n 2 files changed, 67 insertions(+)",
    "diff": "diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c\nindex e697c579be..4ca15bf8f8 100644\n--- a/drivers/net/ice/base/ice_sched.c\n+++ b/drivers/net/ice/base/ice_sched.c\n@@ -3613,6 +3613,70 @@ ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,\n \treturn status;\n }\n \n+/**\n+ * ice_sched_save_q_bw_alloc - save queue node's BW allocation information\n+ * @q_ctx: queue context structure\n+ * @rl_type: rate limit type min, max, or shared\n+ * @bw_alloc: BW weight/allocation\n+ *\n+ * Save BW information of queue type node for post replay use.\n+ */\n+static enum ice_status\n+ice_sched_save_q_bw_alloc(struct ice_q_ctx *q_ctx, enum ice_rl_type rl_type,\n+\t\t\t  u32 bw_alloc)\n+{\n+\tswitch (rl_type) {\n+\tcase ICE_MIN_BW:\n+\t\tice_set_clear_cir_bw_alloc(&q_ctx->bw_t_info, bw_alloc);\n+\t\tbreak;\n+\tcase ICE_MAX_BW:\n+\t\tice_set_clear_eir_bw_alloc(&q_ctx->bw_t_info, bw_alloc);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_cfg_q_bw_alloc - configure queue BW weight/alloc params\n+ * @pi: port information structure\n+ * @vsi_handle: sw VSI handle\n+ * @tc: traffic class\n+ * @q_handle: software queue handle\n+ * @rl_type: min, max, or shared\n+ * @bw_alloc: BW weight/allocation\n+ *\n+ * This function configures BW allocation of queue scheduling node.\n+ */\n+enum ice_status\n+ice_cfg_q_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t   u16 q_handle, enum ice_rl_type rl_type, u32 bw_alloc)\n+{\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\tstruct ice_sched_node *node;\n+\tstruct ice_q_ctx *q_ctx;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\tq_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handle);\n+\tif (!q_ctx)\n+\t\tgoto exit_q_bw_alloc;\n+\n+\tnode = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid);\n+\tif (!node) {\n+\t\tice_debug(pi->hw, ICE_DBG_SCHED, \"Wrong q_teid\\n\");\n+\t\tgoto exit_q_bw_alloc;\n+\t}\n+\n+\tstatus = ice_sched_cfg_node_bw_alloc(pi->hw, node, rl_type, bw_alloc);\n+\tif (!status)\n+\t\tstatus = ice_sched_save_q_bw_alloc(q_ctx, rl_type, bw_alloc);\n+\n+exit_q_bw_alloc:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n /**\n  * ice_cfg_agg_vsi_priority_per_tc - config aggregator's VSI priority per TC\n  * @pi: port information structure\ndiff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h\nindex 1441b5f191..184ad09e6a 100644\n--- a/drivers/net/ice/base/ice_sched.h\n+++ b/drivers/net/ice/base/ice_sched.h\n@@ -172,6 +172,9 @@ enum ice_status\n ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,\n \t\t       u8 *q_prio);\n enum ice_status\n+ice_cfg_q_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t   u16 q_handle, enum ice_rl_type rl_type, u32 bw_alloc);\n+enum ice_status\n ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap,\n \t\t     enum ice_rl_type rl_type, u8 *bw_alloc);\n enum ice_status\n",
    "prefixes": [
        "v9",
        "2/9"
    ]
}