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GET /api/patches/110057/?format=api
{ "id": 110057, "url": "http://patches.dpdk.org/api/patches/110057/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220422014300.2380259-3-wenjun1.wu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220422014300.2380259-3-wenjun1.wu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220422014300.2380259-3-wenjun1.wu@intel.com", "date": "2022-04-22T01:42:59", "name": "[v6,2/3] net/iavf: support queue rate limit configuration", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c15de84e0809e15ac53c798ad63642a51224b16c", "submitter": { "id": 2083, "url": "http://patches.dpdk.org/api/people/2083/?format=api", "name": "Wenjun Wu", "email": "wenjun1.wu@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220422014300.2380259-3-wenjun1.wu@intel.com/mbox/", "series": [ { "id": 22606, "url": "http://patches.dpdk.org/api/series/22606/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22606", "date": "2022-04-22T01:42:58", "name": "Enable queue rate limit and quanta size configuration", "version": 6, "mbox": "http://patches.dpdk.org/series/22606/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/110057/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/110057/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D3E86A0093;\n\tFri, 22 Apr 2022 04:05:11 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7009E427EA;\n\tFri, 22 Apr 2022 04:05:04 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id D4175410D5\n for <dev@dpdk.org>; Fri, 22 Apr 2022 04:05:00 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Apr 2022 19:04:49 -0700", "from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181])\n by orsmga008.jf.intel.com with ESMTP; 21 Apr 2022 19:04:47 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1650593101; x=1682129101;\n h=from:to:subject:date:message-id:in-reply-to:references:\n mime-version:content-transfer-encoding;\n bh=a43Jyx+mVAHdV1ZQSMkoWnk2O0P1JrCL/fGSj+qb128=;\n b=ms6wkIfcdhBefrjM0XLvoIwA6c5eDOmhKLWl1ivS6E4ALB+RIj5Vhrg/\n UoVxyalgjTzOws/K0+b4oX9a6keYDqg0vRlT5u8+eOwAXi/XFLKZcPWH7\n 4VhbxRJxMmGOkVS/Z7Ln7UNTaExp+4pktdq4FIFjkKSk47VbnJVHzBfDe\n dJTYBzFdMuh863aFpP0T0LwJH0NzMF7GNx1qMSgEa6QhwLJKzQhMb841z\n ezQ2RpGY+Lnb2n0jRhMQU7Q3kI9GlWFixKvLTBX7yhkqAHm34GDPJzNYc\n 2UOYR8CdRc4vRIVhG6WUXwdqFVrGekJsVQZ0O0OXlBpnrTa4dOlT6PcOb w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10324\"; a=\"251865599\"", "E=Sophos;i=\"5.90,280,1643702400\"; d=\"scan'208\";a=\"251865599\"", "E=Sophos;i=\"5.90,280,1643702400\"; d=\"scan'208\";a=\"577596600\"" ], "X-ExtLoop1": "1", "From": "Wenjun Wu <wenjun1.wu@intel.com>", "To": "dev@dpdk.org, jingjing.wu@intel.com, beilei.xing@intel.com,\n qi.z.zhang@intel.com", "Subject": "[PATCH v6 2/3] net/iavf: support queue rate limit configuration", "Date": "Fri, 22 Apr 2022 09:42:59 +0800", "Message-Id": "<20220422014300.2380259-3-wenjun1.wu@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220422014300.2380259-1-wenjun1.wu@intel.com>", "References": "<20220329020717.1101263-1-wenjun1.wu@intel.com>\n <20220422014300.2380259-1-wenjun1.wu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds queue rate limit configuration support.\nOnly max bandwidth is supported.\n\nSigned-off-by: Ting Xu <ting.xu@intel.com>\nSigned-off-by: Wenjun Wu <wenjun1.wu@intel.com>\n---\n doc/guides/rel_notes/release_22_07.rst | 3 +\n drivers/net/iavf/iavf.h | 13 ++\n drivers/net/iavf/iavf_tm.c | 190 +++++++++++++++++++++++--\n drivers/net/iavf/iavf_vchnl.c | 23 +++\n 4 files changed, 221 insertions(+), 8 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst\nindex 42a5f2d990..ff379ace67 100644\n--- a/doc/guides/rel_notes/release_22_07.rst\n+++ b/doc/guides/rel_notes/release_22_07.rst\n@@ -55,6 +55,9 @@ New Features\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* **Updated Intel iavf driver.**\n+\n+ * Added Tx QoS queue rate limitation support.\n \n Removed Items\n -------------\ndiff --git a/drivers/net/iavf/iavf.h b/drivers/net/iavf/iavf.h\nindex a01d18e61b..96515a3ee9 100644\n--- a/drivers/net/iavf/iavf.h\n+++ b/drivers/net/iavf/iavf.h\n@@ -170,11 +170,21 @@ struct iavf_tm_node {\n \tuint32_t weight;\n \tuint32_t reference_count;\n \tstruct iavf_tm_node *parent;\n+\tstruct iavf_tm_shaper_profile *shaper_profile;\n \tstruct rte_tm_node_params params;\n };\n \n TAILQ_HEAD(iavf_tm_node_list, iavf_tm_node);\n \n+struct iavf_tm_shaper_profile {\n+\tTAILQ_ENTRY(iavf_tm_shaper_profile) node;\n+\tuint32_t shaper_profile_id;\n+\tuint32_t reference_count;\n+\tstruct rte_tm_shaper_params profile;\n+};\n+\n+TAILQ_HEAD(iavf_shaper_profile_list, iavf_tm_shaper_profile);\n+\n /* node type of Traffic Manager */\n enum iavf_tm_node_type {\n \tIAVF_TM_NODE_TYPE_PORT,\n@@ -188,6 +198,7 @@ struct iavf_tm_conf {\n \tstruct iavf_tm_node *root; /* root node - vf vsi */\n \tstruct iavf_tm_node_list tc_list; /* node list for all the TCs */\n \tstruct iavf_tm_node_list queue_list; /* node list for all the queues */\n+\tstruct iavf_shaper_profile_list shaper_profile_list;\n \tuint32_t nb_tc_node;\n \tuint32_t nb_queue_node;\n \tbool committed;\n@@ -451,6 +462,8 @@ int iavf_add_del_mc_addr_list(struct iavf_adapter *adapter,\n int iavf_request_queues(struct rte_eth_dev *dev, uint16_t num);\n int iavf_get_max_rss_queue_region(struct iavf_adapter *adapter);\n int iavf_get_qos_cap(struct iavf_adapter *adapter);\n+int iavf_set_q_bw(struct rte_eth_dev *dev,\n+\t\t struct virtchnl_queues_bw_cfg *q_bw, uint16_t size);\n int iavf_set_q_tc_map(struct rte_eth_dev *dev,\n \t\t\tstruct virtchnl_queue_tc_mapping *q_tc_mapping,\n \t\t\tuint16_t size);\ndiff --git a/drivers/net/iavf/iavf_tm.c b/drivers/net/iavf/iavf_tm.c\nindex 8d92062c7f..32bb3be45e 100644\n--- a/drivers/net/iavf/iavf_tm.c\n+++ b/drivers/net/iavf/iavf_tm.c\n@@ -8,6 +8,13 @@\n static int iavf_hierarchy_commit(struct rte_eth_dev *dev,\n \t\t\t\t __rte_unused int clear_on_fail,\n \t\t\t\t __rte_unused struct rte_tm_error *error);\n+static int iavf_shaper_profile_add(struct rte_eth_dev *dev,\n+\t\t\t\t uint32_t shaper_profile_id,\n+\t\t\t\t struct rte_tm_shaper_params *profile,\n+\t\t\t\t struct rte_tm_error *error);\n+static int iavf_shaper_profile_del(struct rte_eth_dev *dev,\n+\t\t\t\t uint32_t shaper_profile_id,\n+\t\t\t\t struct rte_tm_error *error);\n static int iavf_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \t uint32_t parent_node_id, uint32_t priority,\n \t uint32_t weight, uint32_t level_id,\n@@ -30,6 +37,8 @@ static int iavf_node_type_get(struct rte_eth_dev *dev, uint32_t node_id,\n \t\t int *is_leaf, struct rte_tm_error *error);\n \n const struct rte_tm_ops iavf_tm_ops = {\n+\t.shaper_profile_add = iavf_shaper_profile_add,\n+\t.shaper_profile_delete = iavf_shaper_profile_del,\n \t.node_add = iavf_tm_node_add,\n \t.node_delete = iavf_tm_node_delete,\n \t.capabilities_get = iavf_tm_capabilities_get,\n@@ -44,6 +53,9 @@ iavf_tm_conf_init(struct rte_eth_dev *dev)\n {\n \tstruct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n \n+\t/* initialize shaper profile list */\n+\tTAILQ_INIT(&vf->tm_conf.shaper_profile_list);\n+\n \t/* initialize node configuration */\n \tvf->tm_conf.root = NULL;\n \tTAILQ_INIT(&vf->tm_conf.tc_list);\n@@ -57,6 +69,7 @@ void\n iavf_tm_conf_uninit(struct rte_eth_dev *dev)\n {\n \tstruct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n+\tstruct iavf_tm_shaper_profile *shaper_profile;\n \tstruct iavf_tm_node *tm_node;\n \n \t/* clear node configuration */\n@@ -74,6 +87,14 @@ iavf_tm_conf_uninit(struct rte_eth_dev *dev)\n \t\trte_free(vf->tm_conf.root);\n \t\tvf->tm_conf.root = NULL;\n \t}\n+\n+\t/* Remove all shaper profiles */\n+\twhile ((shaper_profile =\n+\t TAILQ_FIRST(&vf->tm_conf.shaper_profile_list))) {\n+\t\tTAILQ_REMOVE(&vf->tm_conf.shaper_profile_list,\n+\t\t\t shaper_profile, node);\n+\t\trte_free(shaper_profile);\n+\t}\n }\n \n static inline struct iavf_tm_node *\n@@ -132,13 +153,6 @@ iavf_node_param_check(struct iavf_info *vf, uint32_t node_id,\n \t\treturn -EINVAL;\n \t}\n \n-\t/* not support shaper profile */\n-\tif (params->shaper_profile_id) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_PARAMS_SHAPER_PROFILE_ID;\n-\t\terror->message = \"shaper profile not supported\";\n-\t\treturn -EINVAL;\n-\t}\n-\n \t/* not support shared shaper */\n \tif (params->shared_shaper_id) {\n \t\terror->type = RTE_TM_ERROR_TYPE_NODE_PARAMS_SHARED_SHAPER_ID;\n@@ -236,6 +250,23 @@ iavf_node_type_get(struct rte_eth_dev *dev, uint32_t node_id,\n \treturn 0;\n }\n \n+static inline struct iavf_tm_shaper_profile *\n+iavf_shaper_profile_search(struct rte_eth_dev *dev,\n+\t\t\t uint32_t shaper_profile_id)\n+{\n+\tstruct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n+\tstruct iavf_shaper_profile_list *shaper_profile_list =\n+\t\t&vf->tm_conf.shaper_profile_list;\n+\tstruct iavf_tm_shaper_profile *shaper_profile;\n+\n+\tTAILQ_FOREACH(shaper_profile, shaper_profile_list, node) {\n+\t\tif (shaper_profile_id == shaper_profile->shaper_profile_id)\n+\t\t\treturn shaper_profile;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n static int\n iavf_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \t uint32_t parent_node_id, uint32_t priority,\n@@ -246,6 +277,7 @@ iavf_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \tstruct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n \tenum iavf_tm_node_type node_type = IAVF_TM_NODE_TYPE_MAX;\n \tenum iavf_tm_node_type parent_node_type = IAVF_TM_NODE_TYPE_MAX;\n+\tstruct iavf_tm_shaper_profile *shaper_profile = NULL;\n \tstruct iavf_tm_node *tm_node;\n \tstruct iavf_tm_node *parent_node;\n \tuint16_t tc_nb = vf->qos_cap->num_elem;\n@@ -273,6 +305,18 @@ iavf_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \t\treturn -EINVAL;\n \t}\n \n+\t/* check the shaper profile id */\n+\tif (params->shaper_profile_id != RTE_TM_SHAPER_PROFILE_ID_NONE) {\n+\t\tshaper_profile = iavf_shaper_profile_search(dev,\n+\t\t\tparams->shaper_profile_id);\n+\t\tif (!shaper_profile) {\n+\t\t\terror->type =\n+\t\t\t\tRTE_TM_ERROR_TYPE_NODE_PARAMS_SHAPER_PROFILE_ID;\n+\t\t\terror->message = \"shaper profile not exist\";\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n \t/* root node if not have a parent */\n \tif (parent_node_id == RTE_TM_NODE_ID_NULL) {\n \t\t/* check level */\n@@ -358,6 +402,7 @@ iavf_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \ttm_node->id = node_id;\n \ttm_node->reference_count = 0;\n \ttm_node->parent = parent_node;\n+\ttm_node->shaper_profile = shaper_profile;\n \trte_memcpy(&tm_node->params, params,\n \t\t\t sizeof(struct rte_tm_node_params));\n \tif (parent_node_type == IAVF_TM_NODE_TYPE_PORT) {\n@@ -373,6 +418,10 @@ iavf_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \t}\n \ttm_node->parent->reference_count++;\n \n+\t/* increase the reference counter of the shaper profile */\n+\tif (shaper_profile)\n+\t\tshaper_profile->reference_count++;\n+\n \treturn 0;\n }\n \n@@ -437,6 +486,103 @@ iavf_tm_node_delete(struct rte_eth_dev *dev, uint32_t node_id,\n \treturn 0;\n }\n \n+static int\n+iavf_shaper_profile_param_check(struct rte_tm_shaper_params *profile,\n+\t\t\t\tstruct rte_tm_error *error)\n+{\n+\t/* min bucket size not supported */\n+\tif (profile->committed.size) {\n+\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_SIZE;\n+\t\terror->message = \"committed bucket size not supported\";\n+\t\treturn -EINVAL;\n+\t}\n+\t/* max bucket size not supported */\n+\tif (profile->peak.size) {\n+\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_SIZE;\n+\t\terror->message = \"peak bucket size not supported\";\n+\t\treturn -EINVAL;\n+\t}\n+\t/* length adjustment not supported */\n+\tif (profile->pkt_length_adjust) {\n+\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PKT_ADJUST_LEN;\n+\t\terror->message = \"packet length adjustment not supported\";\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+iavf_shaper_profile_add(struct rte_eth_dev *dev,\n+\t\t\tuint32_t shaper_profile_id,\n+\t\t\tstruct rte_tm_shaper_params *profile,\n+\t\t\tstruct rte_tm_error *error)\n+{\n+\tstruct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n+\tstruct iavf_tm_shaper_profile *shaper_profile;\n+\tint ret;\n+\n+\tif (!profile || !error)\n+\t\treturn -EINVAL;\n+\n+\tret = iavf_shaper_profile_param_check(profile, error);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tshaper_profile = iavf_shaper_profile_search(dev, shaper_profile_id);\n+\n+\tif (shaper_profile) {\n+\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID;\n+\t\terror->message = \"profile ID exist\";\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tshaper_profile = rte_zmalloc(\"iavf_tm_shaper_profile\",\n+\t\t\t\t sizeof(struct iavf_tm_shaper_profile),\n+\t\t\t\t 0);\n+\tif (!shaper_profile)\n+\t\treturn -ENOMEM;\n+\tshaper_profile->shaper_profile_id = shaper_profile_id;\n+\trte_memcpy(&shaper_profile->profile, profile,\n+\t\t\t sizeof(struct rte_tm_shaper_params));\n+\tTAILQ_INSERT_TAIL(&vf->tm_conf.shaper_profile_list,\n+\t\t\t shaper_profile, node);\n+\n+\treturn 0;\n+}\n+\n+static int\n+iavf_shaper_profile_del(struct rte_eth_dev *dev,\n+\t\t\tuint32_t shaper_profile_id,\n+\t\t\tstruct rte_tm_error *error)\n+{\n+\tstruct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n+\tstruct iavf_tm_shaper_profile *shaper_profile;\n+\n+\tif (!error)\n+\t\treturn -EINVAL;\n+\n+\tshaper_profile = iavf_shaper_profile_search(dev, shaper_profile_id);\n+\n+\tif (!shaper_profile) {\n+\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID;\n+\t\terror->message = \"profile ID not exist\";\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* don't delete a profile if it's used by one or several nodes */\n+\tif (shaper_profile->reference_count) {\n+\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE;\n+\t\terror->message = \"profile in use\";\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tTAILQ_REMOVE(&vf->tm_conf.shaper_profile_list, shaper_profile, node);\n+\trte_free(shaper_profile);\n+\n+\treturn 0;\n+}\n+\n static int\n iavf_tm_capabilities_get(struct rte_eth_dev *dev,\n \t\t\t struct rte_tm_capabilities *cap,\n@@ -656,10 +802,11 @@ static int iavf_hierarchy_commit(struct rte_eth_dev *dev,\n \tstruct iavf_adapter *adapter =\n \t\tIAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n \tstruct virtchnl_queue_tc_mapping *q_tc_mapping;\n+\tstruct virtchnl_queues_bw_cfg *q_bw;\n \tstruct iavf_tm_node_list *queue_list = &vf->tm_conf.queue_list;\n \tstruct iavf_tm_node *tm_node;\n \tstruct iavf_qtc_map *qtc_map;\n-\tuint16_t size;\n+\tuint16_t size, size_q;\n \tint index = 0, node_committed = 0;\n \tint i, ret_val = IAVF_SUCCESS;\n \n@@ -691,10 +838,21 @@ static int iavf_hierarchy_commit(struct rte_eth_dev *dev,\n \t\tgoto fail_clear;\n \t}\n \n+\tsize_q = sizeof(*q_bw) + sizeof(q_bw->cfg[0]) *\n+\t\t(vf->num_queue_pairs - 1);\n+\tq_bw = rte_zmalloc(\"q_bw\", size_q, 0);\n+\tif (!q_bw) {\n+\t\tret_val = IAVF_ERR_NO_MEMORY;\n+\t\tgoto fail_clear;\n+\t}\n+\n \tq_tc_mapping->vsi_id = vf->vsi.vsi_id;\n \tq_tc_mapping->num_tc = vf->qos_cap->num_elem;\n \tq_tc_mapping->num_queue_pairs = vf->num_queue_pairs;\n \n+\tq_bw->vsi_id = vf->vsi.vsi_id;\n+\tq_bw->num_queues = vf->num_queue_pairs;\n+\n \tTAILQ_FOREACH(tm_node, queue_list, node) {\n \t\tif (tm_node->tc >= q_tc_mapping->num_tc) {\n \t\t\tPMD_DRV_LOG(ERR, \"TC%d is not enabled\", tm_node->tc);\n@@ -702,6 +860,18 @@ static int iavf_hierarchy_commit(struct rte_eth_dev *dev,\n \t\t\tgoto fail_clear;\n \t\t}\n \t\tq_tc_mapping->tc[tm_node->tc].req.queue_count++;\n+\n+\t\tif (tm_node->shaper_profile) {\n+\t\t\tq_bw->cfg[node_committed].queue_id = node_committed;\n+\t\t\tq_bw->cfg[node_committed].shaper.peak =\n+\t\t\ttm_node->shaper_profile->profile.peak.rate /\n+\t\t\t1000 * IAVF_BITS_PER_BYTE;\n+\t\t\tq_bw->cfg[node_committed].shaper.committed =\n+\t\t\ttm_node->shaper_profile->profile.committed.rate /\n+\t\t\t1000 * IAVF_BITS_PER_BYTE;\n+\t\t\tq_bw->cfg[node_committed].tc = tm_node->tc;\n+\t\t}\n+\n \t\tnode_committed++;\n \t}\n \n@@ -712,6 +882,10 @@ static int iavf_hierarchy_commit(struct rte_eth_dev *dev,\n \t\tgoto fail_clear;\n \t}\n \n+\tret_val = iavf_set_q_bw(dev, q_bw, size_q);\n+\tif (ret_val)\n+\t\tgoto fail_clear;\n+\n \t/* store the queue TC mapping info */\n \tqtc_map = rte_zmalloc(\"qtc_map\",\n \t\tsizeof(struct iavf_qtc_map) * q_tc_mapping->num_tc, 0);\ndiff --git a/drivers/net/iavf/iavf_vchnl.c b/drivers/net/iavf/iavf_vchnl.c\nindex 169e1f2012..537369f736 100644\n--- a/drivers/net/iavf/iavf_vchnl.c\n+++ b/drivers/net/iavf/iavf_vchnl.c\n@@ -1636,6 +1636,29 @@ int iavf_set_q_tc_map(struct rte_eth_dev *dev,\n \treturn err;\n }\n \n+int iavf_set_q_bw(struct rte_eth_dev *dev,\n+\t\tstruct virtchnl_queues_bw_cfg *q_bw, uint16_t size)\n+{\n+\tstruct iavf_adapter *adapter =\n+\t\t\tIAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tstruct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n+\tstruct iavf_cmd_info args;\n+\tint err;\n+\n+\tmemset(&args, 0, sizeof(args));\n+\targs.ops = VIRTCHNL_OP_CONFIG_QUEUE_BW;\n+\targs.in_args = (uint8_t *)q_bw;\n+\targs.in_args_size = size;\n+\targs.out_buffer = vf->aq_resp;\n+\targs.out_size = IAVF_AQ_BUF_SZ;\n+\n+\terr = iavf_execute_vf_cmd(adapter, &args, 0);\n+\tif (err)\n+\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of\"\n+\t\t\t \" VIRTCHNL_OP_CONFIG_QUEUE_BW\");\n+\treturn err;\n+}\n+\n int\n iavf_add_del_mc_addr_list(struct iavf_adapter *adapter,\n \t\t\tstruct rte_ether_addr *mc_addrs,\n", "prefixes": [ "v6", "2/3" ] }