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GET /api/patches/109814/?format=api
{ "id": 109814, "url": "http://patches.dpdk.org/api/patches/109814/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220419055921.10566-9-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220419055921.10566-9-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220419055921.10566-9-ndabilpuram@marvell.com", "date": "2022-04-19T05:59:06", "name": "[09/24] common/cnxk: use aggregate level rr prio from mbox", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9be0ca31dc82b6d9db4a2f5727aeb1214c60ab85", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220419055921.10566-9-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 22546, "url": "http://patches.dpdk.org/api/series/22546/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22546", "date": "2022-04-19T05:58:58", "name": "[01/24] common/cnxk: add multi channel support for SDP send queues", "version": 1, "mbox": "http://patches.dpdk.org/series/22546/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/109814/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/109814/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 47E14A00C3;\n\tTue, 19 Apr 2022 08:00:57 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B2C4C42805;\n\tTue, 19 Apr 2022 08:00:23 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id CA11741156\n for <dev@dpdk.org>; Tue, 19 Apr 2022 08:00:21 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 23INEdMW010013\n for <dev@dpdk.org>; Mon, 18 Apr 2022 23:00:21 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ffwap25vx-9\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 18 Apr 2022 23:00:21 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 18 Apr 2022 23:00:19 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 18 Apr 2022 23:00:19 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 1C60E5B6948;\n Mon, 18 Apr 2022 23:00:16 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=v1RGzXhGI7uoQ7jftU7Zl6FD8DcQLqM7OnfiPOAidxQ=;\n b=L5z74ydWmWgIy/pafWvD1drCvpfNDDF4x8/SDHJwusiyqMNOVQwqh9C7C2X89B48QIWU\n 9FJQJFdIEzWFVtyTe3i5dIk9HBpkUtC7pmLwAr4dPKcv4LKXUb7tNYKiPpjVhKnZuQgQ\n MnTUZ0e6UzIl05PsVMrvOSLQ+Agp69FHhaSoMiNJNrlpks0VrrauKJAxng7k3n7g+uMr\n ZrlTvfSuhQAv8FDKMt2Qg5QE3EVACPMwMm9ZtULHU8VDvpfdhAovoVjjkj2OGz932H9F\n 5UnXhCIPYIY9uiOFx/cmzCqCIO1D8TNI7SFp0sN39ozpaLMSi+vqBfXd6xwlGM+afzsB AA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 09/24] common/cnxk: use aggregate level rr prio from mbox", "Date": "Tue, 19 Apr 2022 11:29:06 +0530", "Message-ID": "<20220419055921.10566-9-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220419055921.10566-1-ndabilpuram@marvell.com>", "References": "<20220419055921.10566-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "ECbQwi-hXRCXmhgPiBPJ1KDk-eYZxlEB", "X-Proofpoint-ORIG-GUID": "ECbQwi-hXRCXmhgPiBPJ1KDk-eYZxlEB", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514\n definitions=2022-04-19_02,2022-04-15_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Use aggregate level Round Robin Priority from mbox response instead of\nfixing it to single macro. This is useful when kernel AF driver\nchanges the constant.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix_priv.h | 5 +++--\n drivers/common/cnxk/roc_nix_tm.c | 3 ++-\n drivers/common/cnxk/roc_nix_tm_utils.c | 8 ++++----\n 3 files changed, 9 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 9b9ffae..cc69d71 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -181,6 +181,7 @@ struct nix {\n \tuint16_t tm_root_lvl;\n \tuint16_t tm_flags;\n \tuint16_t tm_link_cfg_lvl;\n+\tuint8_t tm_aggr_lvl_rr_prio;\n \tuint16_t contig_rsvd[NIX_TXSCH_LVL_CNT];\n \tuint16_t discontig_rsvd[NIX_TXSCH_LVL_CNT];\n \tuint64_t tm_markfmt_en;\n@@ -284,7 +285,6 @@ void nix_unregister_irqs(struct nix *nix);\n \n /* Default TL1 priority and Quantum from AF */\n #define NIX_TM_TL1_DFLT_RR_QTM\t((1 << 24) - 1)\n-#define NIX_TM_TL1_DFLT_RR_PRIO 1\n \n struct nix_tm_shaper_data {\n \tuint64_t burst_exponent;\n@@ -432,7 +432,8 @@ bool nix_tm_child_res_valid(struct nix_tm_node_list *list,\n \t\t\t struct nix_tm_node *parent);\n uint16_t nix_tm_resource_estimate(struct nix *nix, uint16_t *schq_contig,\n \t\t\t\t uint16_t *schq, enum roc_nix_tm_tree tree);\n-uint8_t nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg,\n+uint8_t nix_tm_tl1_default_prep(struct nix *nix, uint32_t schq,\n+\t\t\t\tvolatile uint64_t *reg,\n \t\t\t\tvolatile uint64_t *regval);\n uint8_t nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,\n \t\t\t\t volatile uint64_t *reg,\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex 42d3abd..7fd54ef 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -55,7 +55,7 @@ nix_tm_node_reg_conf(struct nix *nix, struct nix_tm_node *node)\n \t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n \t\treq->lvl = NIX_TXSCH_LVL_TL1;\n \n-\t\tk = nix_tm_tl1_default_prep(node->parent_hw_id, req->reg,\n+\t\tk = nix_tm_tl1_default_prep(nix, node->parent_hw_id, req->reg,\n \t\t\t\t\t req->regval);\n \t\treq->num_regs = k;\n \t\trc = mbox_process(mbox);\n@@ -1288,6 +1288,7 @@ nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree)\n \t} while (pend);\n \n \tnix->tm_link_cfg_lvl = rsp->link_cfg_lvl;\n+\tnix->tm_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio;\n \treturn 0;\n alloc_err:\n \tfor (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {\ndiff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c\nindex bcdf990..b9b605f 100644\n--- a/drivers/common/cnxk/roc_nix_tm_utils.c\n+++ b/drivers/common/cnxk/roc_nix_tm_utils.c\n@@ -478,7 +478,7 @@ nix_tm_child_res_valid(struct nix_tm_node_list *list,\n }\n \n uint8_t\n-nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg,\n+nix_tm_tl1_default_prep(struct nix *nix, uint32_t schq, volatile uint64_t *reg,\n \t\t\tvolatile uint64_t *regval)\n {\n \tuint8_t k = 0;\n@@ -496,7 +496,7 @@ nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg,\n \tk++;\n \n \treg[k] = NIX_AF_TL1X_TOPOLOGY(schq);\n-\tregval[k] = (NIX_TM_TL1_DFLT_RR_PRIO << 1);\n+\tregval[k] = (nix->tm_aggr_lvl_rr_prio << 1);\n \tk++;\n \n \treg[k] = NIX_AF_TL1X_CIR(schq);\n@@ -540,7 +540,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,\n \t * Static Priority is disabled\n \t */\n \tif (hw_lvl == NIX_TXSCH_LVL_TL1 && nix->tm_flags & NIX_TM_TL1_NO_SP) {\n-\t\trr_prio = NIX_TM_TL1_DFLT_RR_PRIO;\n+\t\trr_prio = nix->tm_aggr_lvl_rr_prio;\n \t\tchild = 0;\n \t}\n \n@@ -662,7 +662,7 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node,\n \t */\n \tif (hw_lvl == NIX_TXSCH_LVL_TL2 &&\n \t (!nix_tm_have_tl1_access(nix) || nix->tm_flags & NIX_TM_TL1_NO_SP))\n-\t\tstrict_prio = NIX_TM_TL1_DFLT_RR_PRIO;\n+\t\tstrict_prio = nix->tm_aggr_lvl_rr_prio;\n \n \tplt_tm_dbg(\"Schedule config node %s(%u) lvl %u id %u, \"\n \t\t \"prio 0x%\" PRIx64 \", rr_quantum/rr_wt 0x%\" PRIx64 \" (%p)\",\n", "prefixes": [ "09/24" ] }