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GET /api/patches/109622/?format=api
{ "id": 109622, "url": "http://patches.dpdk.org/api/patches/109622/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220412174224.13143-1-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220412174224.13143-1-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220412174224.13143-1-syalavarthi@marvell.com", "date": "2022-04-12T17:42:24", "name": "[1/1] common/cnxk: added new macros to platform layer", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9a78f7724079fcea2219c4ab10ce2d9c089fcc15", "submitter": { "id": 2480, "url": "http://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220412174224.13143-1-syalavarthi@marvell.com/mbox/", "series": [ { "id": 22491, "url": "http://patches.dpdk.org/api/series/22491/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22491", "date": "2022-04-12T17:42:24", "name": "[1/1] common/cnxk: added new macros to platform layer", "version": 1, "mbox": "http://patches.dpdk.org/series/22491/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/109622/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/109622/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7E500A0505;\n\tTue, 12 Apr 2022 19:42:53 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 868E241611;\n\tTue, 12 Apr 2022 19:42:46 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id E8D5B41611\n for <dev@dpdk.org>; Tue, 12 Apr 2022 19:42:44 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 23CG37dI025894\n for <dev@dpdk.org>; Tue, 12 Apr 2022 10:42:44 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3fb9nnnynj-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 12 Apr 2022 10:42:44 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 12 Apr 2022 10:42:42 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 12 Apr 2022 10:42:42 -0700", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id F2C823F705A;\n Tue, 12 Apr 2022 10:42:41 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-type; s=pfpt0220;\n bh=0Jk+v9n5vMAxkI0d1eYJTRPUImabJAhyMeXLQDxa9es=;\n b=Qs62FwyN92iHnobeWs8mwHNO5c28LoIM7v6P39vjSXARPjSe2mnLccJMr2ec7PY287ZY\n v2YcLQzuDlYRHO43cvEVXPnx22aloNeis4Y0VZq0bTPvuHL/9XJyPwPQs1PkmK4otFLL\n COeKPh5Fd6o/WjXLiZwyKkJuCejaQ5yyPtdcV5JM+WXqoRfd4tMlhJbhmSsrMFqmGhcF\n P/20IlqiypWAQCZlt5/OgKUz9le4qQd4ee9PGJq7Q9DohB+QeVBHfY9OuNv1kr2zwElr\n 8wbifeFRlpL/dj88b0mck1iVxR080nY8YvcP0cQJm8klZdYaPc6GosIbWffi81xEwXKR SQ==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, <jerinj@marvell.com>, <sshankarnara@marvell.com>,\n \"Srikanth Yalavarthi\" <syalavarthi@marvell.com>", "Subject": "[PATCH 1/1] common/cnxk: added new macros to platform layer", "Date": "Tue, 12 Apr 2022 10:42:24 -0700", "Message-ID": "<20220412174224.13143-1-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "5IJaR1p5SpwarvxnoEbKIacaf70Xos_7", "X-Proofpoint-GUID": "5IJaR1p5SpwarvxnoEbKIacaf70Xos_7", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514\n definitions=2022-04-12_06,2022-04-12_02,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added new macros for pointer operations, bitwise operations,\nspinlocks and 32 bit read and write.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/common/cnxk/roc_bits.h | 12 ++++++++++++\n drivers/common/cnxk/roc_platform.h | 28 +++++++++++++++++++---------\n 2 files changed, 31 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_bits.h b/drivers/common/cnxk/roc_bits.h\nindex 11216d9d63..ce3dffa08d 100644\n--- a/drivers/common/cnxk/roc_bits.h\n+++ b/drivers/common/cnxk/roc_bits.h\n@@ -29,4 +29,16 @@\n \t (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))\n #endif\n \n+#ifndef IS_BIT_SET\n+#define IS_BIT_SET(num, n) ((num) & (1 << (n)))\n+#endif\n+\n+#ifndef SET_BIT\n+#define SET_BIT(num, n) ((num) | (1 << (n)))\n+#endif\n+\n+#ifndef CLEAR_BIT\n+#define CLEAR_BIT(num, n) ((num) &= ~((1) << (n)))\n+#endif\n+\n #endif /* _ROC_BITS_H_ */\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 28004b1743..3671e55c23 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -41,6 +41,7 @@\n #define PLT_MEMZONE_NAMESIZE\t RTE_MEMZONE_NAMESIZE\n #define PLT_STD_C11\t\t RTE_STD_C11\n #define PLT_PTR_ADD\t\t RTE_PTR_ADD\n+#define PLT_PTR_SUB\t\t RTE_PTR_SUB\n #define PLT_PTR_DIFF\t\t RTE_PTR_DIFF\n #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID\n #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET\n@@ -70,12 +71,16 @@\n #define PLT_U32_CAST(val) ((uint32_t)(val))\n #define PLT_U16_CAST(val) ((uint16_t)(val))\n \n+/* Add / Sub pointer with scalar and cast to uint64_t */\n+#define PLT_PTR_ADD_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_ADD(__ptr, __x))\n+#define PLT_PTR_SUB_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_SUB(__ptr, __x))\n+\n /** Divide ceil */\n-#define PLT_DIV_CEIL(x, y)\t\t\t\\\n-\t({\t\t\t\t\t\\\n-\t\t__typeof(x) __x = x;\t\t\\\n-\t\t__typeof(y) __y = y;\t\t\\\n-\t\t(__x + __y - 1) / __y;\t\t\\\n+#define PLT_DIV_CEIL(x, y) \\\n+\t({ \\\n+\t\t__typeof(x) __x = x; \\\n+\t\t__typeof(y) __y = y; \\\n+\t\t(__x + __y - 1) / __y; \\\n \t})\n \n #define __plt_cache_aligned __rte_cache_aligned\n@@ -113,10 +118,11 @@\n #define plt_bitmap_scan\t\t\trte_bitmap_scan\n #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint\n \n-#define plt_spinlock_t\t rte_spinlock_t\n-#define plt_spinlock_init rte_spinlock_init\n-#define plt_spinlock_lock rte_spinlock_lock\n-#define plt_spinlock_unlock rte_spinlock_unlock\n+#define plt_spinlock_t\t rte_spinlock_t\n+#define plt_spinlock_init rte_spinlock_init\n+#define plt_spinlock_lock rte_spinlock_lock\n+#define plt_spinlock_unlock rte_spinlock_unlock\n+#define plt_spinlock_trylock rte_spinlock_trylock\n \n #define plt_intr_callback_register rte_intr_callback_register\n #define plt_intr_callback_unregister rte_intr_callback_unregister\n@@ -165,6 +171,10 @@\n #define plt_write64(val, addr) \\\n \trte_write64_relaxed((val), (volatile void *)(addr))\n \n+#define plt_read32(addr) rte_read32_relaxed((volatile void *)(addr))\n+#define plt_write32(val, addr) \\\n+\trte_write32_relaxed((val), (volatile void *)(addr))\n+\n #define plt_wmb()\t\trte_wmb()\n #define plt_rmb()\t\trte_rmb()\n #define plt_io_wmb()\t\trte_io_wmb()\n", "prefixes": [ "1/1" ] }