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GET /api/patches/108861/?format=api
{ "id": 108861, "url": "http://patches.dpdk.org/api/patches/108861/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220325105939.1117634-1-vfialko@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220325105939.1117634-1-vfialko@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220325105939.1117634-1-vfialko@marvell.com", "date": "2022-03-25T10:59:39", "name": "event/cnxk: fix base pointer for SSO head wait", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "cb79b1b433d9602ff73f5819fbf4165373fab553", "submitter": { "id": 2390, "url": "http://patches.dpdk.org/api/people/2390/?format=api", "name": "Volodymyr Fialko", "email": "vfialko@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220325105939.1117634-1-vfialko@marvell.com/mbox/", "series": [ { "id": 22241, "url": "http://patches.dpdk.org/api/series/22241/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22241", "date": "2022-03-25T10:59:39", "name": "event/cnxk: fix base pointer for SSO head wait", "version": 1, "mbox": "http://patches.dpdk.org/series/22241/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/108861/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/108861/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7EB17A00C3;\n\tFri, 25 Mar 2022 11:59:56 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1F9CC40687;\n\tFri, 25 Mar 2022 11:59:56 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 02D1240140;\n Fri, 25 Mar 2022 11:59:54 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 22P5xHF4022917;\n Fri, 25 Mar 2022 03:59:54 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3f0mn6x44r-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Fri, 25 Mar 2022 03:59:54 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 25 Mar 2022 03:59:52 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 25 Mar 2022 03:59:52 -0700", "from localhost.localdomain (unknown [10.28.34.39])\n by maili.marvell.com (Postfix) with ESMTP id 024C33F704C;\n Fri, 25 Mar 2022 03:59:49 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=P9fLK8OCVfLcLW2tlPqvRlhxZYRsj/lapQIF4KlP8jw=;\n b=b/N2BlzkZJgq5ZMsuTeBg2uWUghWJ4yfIPY58XIObRvfZrNB423NtNUbg+0s52rFCmX9\n nLf66DJkOeYhuwKwRF1XG2Va116COOw9V26P7B/1WslSqgoeaR7XXVN1G5RqZ7+hUTx6\n RwxVY1bUWAoFfo6lybbdR38eY/0malEm53tkY8zzGX5GW1930T/ridylZZGip6vThVSa\n eQqGnuM2fP2tUJXWdrKNBU6MsZBpt5PgnSCbXmZj/X+cvAET1NtL7It9TW8I/cuw13Gk\n 9DIRSEnCfzUR0Ss/vI+AfcbHnuCBqhrEA3qkd73a5v8rw7ntL8B/KVUveGa3c3rtMJYV xQ==", "From": "Volodymyr Fialko <vfialko@marvell.com>", "To": "<dev@dpdk.org>, Ankur Dwivedi <adwivedi@marvell.com>, Anoob Joseph\n <anoobj@marvell.com>, Tejasree Kondoj <ktejasree@marvell.com>, \"Pavan\n Nikhilesh\" <pbhagavatula@marvell.com>,\n Shijith Thotton <sthotton@marvell.com>", "CC": "<jerinj@marvell.com>, Volodymyr Fialko <vfialko@marvell.com>,\n <stable@dpdk.org>", "Subject": "[PATCH] event/cnxk: fix base pointer for SSO head wait", "Date": "Fri, 25 Mar 2022 11:59:39 +0100", "Message-ID": "<20220325105939.1117634-1-vfialko@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "KX_LL-p8bCXY_ZfEze8HWtcxjOd5PptF", "X-Proofpoint-ORIG-GUID": "KX_LL-p8bCXY_ZfEze8HWtcxjOd5PptF", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514\n definitions=2022-03-25_02,2022-03-24_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Function roc_sso_hws_head_wait() expects a base as input pointer, and it\nwill itself get tag_op from the base. By passing tag_op instead of base\npointer to this function will add SSOW_LF_GWS_TAG register offset twice,\nwhich will lead to accessing wrong register.\n\nFixes: 1f5b3d55c041 (\"event/cnxk: store and reuse workslot status\")\n\nCc: stable@dpdk.org\n\nSigned-off-by: Volodymyr Fialko <vfialko@marvell.com>\n---\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 4 ++--\n drivers/crypto/cnxk/cn10k_cryptodev_ops.h | 2 +-\n drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 4 ++--\n drivers/crypto/cnxk/cn9k_cryptodev_ops.h | 2 +-\n drivers/event/cnxk/cn10k_worker.c | 3 +--\n drivers/event/cnxk/cn9k_worker.c | 7 +++----\n 6 files changed, 10 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex d217bbf383..1b08c67fea 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -265,7 +265,7 @@ cn10k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n }\n \n uint16_t\n-cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)\n+cn10k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op)\n {\n \tunion rte_event_crypto_metadata *ec_mdata;\n \tstruct cpt_inflight_req *infl_req;\n@@ -328,7 +328,7 @@ cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)\n \t}\n \n \tif (!rsp_info->sched_type)\n-\t\troc_sso_hws_head_wait(tag_op);\n+\t\troc_sso_hws_head_wait(base);\n \n \tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id;\n \troc_lmt_submit_steorl(lmt_arg, qp->lmtline.io_addr);\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h\nindex d7e9f87396..1ad4c16873 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h\n@@ -13,7 +13,7 @@ extern struct rte_cryptodev_ops cn10k_cpt_ops;\n void cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);\n \n __rte_internal\n-uint16_t cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op,\n+uint16_t cn10k_cpt_crypto_adapter_enqueue(uintptr_t base,\n \t\t\t\t\t struct rte_crypto_op *op);\n __rte_internal\n uintptr_t cn10k_cpt_crypto_adapter_dequeue(uintptr_t get_work1);\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\nindex ddba9d5dd0..d3858149c7 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n@@ -317,7 +317,7 @@ cn9k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n }\n \n uint16_t\n-cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)\n+cn9k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op)\n {\n \tunion rte_event_crypto_metadata *ec_mdata;\n \tstruct cpt_inflight_req *infl_req;\n@@ -374,7 +374,7 @@ cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)\n \t}\n \n \tif (!rsp_info->sched_type)\n-\t\troc_sso_hws_head_wait(tag_op);\n+\t\troc_sso_hws_head_wait(base);\n \n \tcn9k_cpt_inst_submit(&inst, qp->lmtline.lmt_base, qp->lmtline.io_addr);\n \ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.h b/drivers/crypto/cnxk/cn9k_cryptodev_ops.h\nindex 309f507346..9f6dc24603 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.h\n@@ -12,7 +12,7 @@ extern struct rte_cryptodev_ops cn9k_cpt_ops;\n void cn9k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);\n \n __rte_internal\n-uint16_t cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op,\n+uint16_t cn9k_cpt_crypto_adapter_enqueue(uintptr_t base,\n \t\t\t\t\t struct rte_crypto_op *op);\n __rte_internal\n uintptr_t cn9k_cpt_crypto_adapter_dequeue(uintptr_t get_work1);\ndiff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c\nindex 975a22336a..1ffd48a5ab 100644\n--- a/drivers/event/cnxk/cn10k_worker.c\n+++ b/drivers/event/cnxk/cn10k_worker.c\n@@ -68,6 +68,5 @@ cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)\n \n \tRTE_SET_USED(nb_events);\n \n-\treturn cn10k_cpt_crypto_adapter_enqueue(ws->base + SSOW_LF_GWS_TAG,\n-\t\t\t\t\t\tev->event_ptr);\n+\treturn cn10k_cpt_crypto_adapter_enqueue(ws->base, ev->event_ptr);\n }\ndiff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c\nindex a981bc986f..fca1f0dffa 100644\n--- a/drivers/event/cnxk/cn9k_worker.c\n+++ b/drivers/event/cnxk/cn9k_worker.c\n@@ -128,8 +128,7 @@ cn9k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)\n \n \tRTE_SET_USED(nb_events);\n \n-\treturn cn9k_cpt_crypto_adapter_enqueue(ws->base + SSOW_LF_GWS_TAG,\n-\t\t\t\t\t ev->event_ptr);\n+\treturn cn9k_cpt_crypto_adapter_enqueue(ws->base, ev->event_ptr);\n }\n \n uint16_t __rte_hot\n@@ -139,6 +138,6 @@ cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)\n \n \tRTE_SET_USED(nb_events);\n \n-\treturn cn9k_cpt_crypto_adapter_enqueue(\n-\t\tdws->base[!dws->vws] + SSOW_LF_GWS_TAG, ev->event_ptr);\n+\treturn cn9k_cpt_crypto_adapter_enqueue(dws->base[!dws->vws],\n+\t\t\t\t\t ev->event_ptr);\n }\n", "prefixes": [] }