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GET /api/patches/108215/?format=api
{ "id": 108215, "url": "http://patches.dpdk.org/api/patches/108215/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220224031029.14049-13-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220224031029.14049-13-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220224031029.14049-13-suanmingm@nvidia.com", "date": "2022-02-24T03:10:27", "name": "[v3,12/14] net/mlx5: add mark action", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d6bbd9111210ae8ae4367b916657301b711efc77", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220224031029.14049-13-suanmingm@nvidia.com/mbox/", "series": [ { "id": 21839, "url": "http://patches.dpdk.org/api/series/21839/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21839", "date": "2022-02-24T03:10:16", "name": "net/mlx5: add hardware steering", "version": 3, "mbox": "http://patches.dpdk.org/series/21839/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/108215/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/108215/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 56EB4A0353;\n\tThu, 24 Feb 2022 04:12:22 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B7321426D7;\n\tThu, 24 Feb 2022 04:11:25 +0100 (CET)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2049.outbound.protection.outlook.com [40.107.93.49])\n by mails.dpdk.org (Postfix) with ESMTP id 17D3141C25\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH v3 12/14] net/mlx5: add mark action", "Date": "Thu, 24 Feb 2022 05:10:27 +0200", "Message-ID": "<20220224031029.14049-13-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220224031029.14049-1-suanmingm@nvidia.com>", "References": "<20220210162926.20436-1-suanmingm@nvidia.com>\n <20220224031029.14049-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "5fcef6ff-7313-4641-a6b5-08d9f7435366", "X-MS-TrafficTypeDiagnostic": "LV2PR12MB5774:EE_", "X-Microsoft-Antispam-PRVS": "\n <LV2PR12MB5774461132BC6D753E059B34C13D9@LV2PR12MB5774.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 2MZ187wPG9EnV/aB/N99/HbsB0eDdS7/gITAHQ/wSRhnNn3Gc2505azUqv8m4FJvYQMMHEip120uMI6zoqhiP49BL7ujOLWu25ddW/4qDMWRJ3J44DH4Eah6gtmY3WZ0VIaWPNH/U9XHL0ytft1kNT1Yslu255SSkyFB08WnrlxmlnXYp0g0/s30soZw0zR3QhS1zIEv1CXHRuBYlRspAEBgl61DIiGlT1+eexwZQ+4dVODKhYQKc/+AUURtJK+f5OX7jvuEH02fo0uiZN/Gti80MAs9wLGbabZ2axOh3QFWOAdlqMzmoeEgSouI3/hQ1/73q2HznR+gKwXlLtLZQcTeJuIKn0uLVosxhbtfTvuFFPFV0J0y7JsGUz4cA2uq2prXePjgMuKbAVi0wyo35n/rdC1NzhKOnE/IfE3kFmjU+sJXWU1c1npFheJiQvHM8y03XyQhjmKs7Dd1PQKs89bzsUxIlgWjUgrbeM9S3V3bABZopCglPwy64O/9FtXKvmbtCM9OGBNPsFT8aoezQXQ5aNYn2lXEJOtv0URqZT4rLL3VTrWcnNjvftzpsJCIOzRraRezAmy57HwRic5OsdrDxQNZ+1FceHFv4OU4gHNsYhYFZ9QY/o9Wgyk1NdwAG3Wq2A3AJJw/VXWWfsrExU/Q2SXQPGRihh2QW6eJdQaTckj74FQHMfy3BkRlqUjWAn3BVrAiu9N0U+fAoABrjw==", "X-Forefront-Antispam-Report": "CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(7696005)(186003)(356005)(55016003)(16526019)(316002)(336012)(26005)(6636002)(54906003)(2616005)(86362001)(6286002)(1076003)(110136005)(82310400004)(426003)(81166007)(508600001)(40460700003)(6666004)(36860700001)(36756003)(83380400001)(8676002)(2906002)(8936002)(70206006)(5660300002)(4326008)(47076005)(70586007)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Feb 2022 03:11:18.2491 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5fcef6ff-7313-4641-a6b5-08d9f7435366", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT035.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV2PR12MB5774", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The mark action is covered by tag action internally. While it is added\nthe HW will add a tag to the packet. The mark value can be set as fixed\nor dynamic as the action mask indicates.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 2 +\n drivers/net/mlx5/mlx5_flow.h | 1 +\n drivers/net/mlx5/mlx5_flow_hw.c | 66 ++++++++++++++++++++++++++++++---\n 3 files changed, 63 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex f60a40d669..a0f9fbe365 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1531,6 +1531,8 @@ struct mlx5_priv {\n \t/* HW steering global drop action. */\n \tstruct mlx5dr_action *hw_drop[MLX5_HW_ACTION_FLAG_MAX]\n \t\t\t\t [MLX5DR_TABLE_TYPE_MAX];\n+\t/* HW steering global drop action. */\n+\tstruct mlx5dr_action *hw_tag[MLX5_HW_ACTION_FLAG_MAX];\n \tstruct mlx5_indexed_pool *acts_ipool; /* Action data indexed pool. */\n #endif\n };\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 70e6cf633f..c83e73c793 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1077,6 +1077,7 @@ struct mlx5_hw_actions {\n \tstruct mlx5_hw_jump_action *jump; /* Jump action. */\n \tstruct mlx5_hrxq *tir; /* TIR action. */\n \tuint32_t acts_num:4; /* Total action number. */\n+\tuint32_t mark:1; /* Indicate the mark action. */\n \t/* Translated DR action array from action template. */\n \tstruct mlx5dr_rule_action rule_acts[MLX5_HW_MAX_ACTS];\n };\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 0d49ab0bb2..a28e3c00b3 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -37,6 +37,31 @@ static uint32_t mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_MAX]\n \t},\n };\n \n+/**\n+ * Set rxq flag.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[in] enable\n+ * Flag to enable or not.\n+ */\n+static void\n+flow_hw_rxq_flag_set(struct rte_eth_dev *dev, bool enable)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tunsigned int i;\n+\n+\tif ((!priv->mark_enabled && !enable) ||\n+\t (priv->mark_enabled && enable))\n+\t\treturn;\n+\tfor (i = 0; i < priv->rxqs_n; ++i) {\n+\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i);\n+\n+\t\trxq_ctrl->rxq.mark = enable;\n+\t}\n+\tpriv->mark_enabled = enable;\n+}\n+\n /**\n * Register destination table DR jump action.\n *\n@@ -298,6 +323,20 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\tacts->rule_acts[i++].action =\n \t\t\t\tpriv->hw_drop[!!attr->group][type];\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_MARK:\n+\t\t\tacts->mark = true;\n+\t\t\tif (masks->conf)\n+\t\t\t\tacts->rule_acts[i].tag.value =\n+\t\t\t\t\tmlx5_flow_mark_set\n+\t\t\t\t\t(((const struct rte_flow_action_mark *)\n+\t\t\t\t\t(masks->conf))->id);\n+\t\t\telse if (__flow_hw_act_data_general_append(priv, acts,\n+\t\t\t\tactions->type, actions - action_start, i))\n+\t\t\t\tgoto err;\n+\t\t\tacts->rule_acts[i++].action =\n+\t\t\t\tpriv->hw_tag[!!attr->group];\n+\t\t\tflow_hw_rxq_flag_set(dev, true);\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_JUMP:\n \t\t\tif (masks->conf) {\n \t\t\t\tuint32_t jump_group =\n@@ -424,6 +463,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t}\n \tLIST_FOREACH(act_data, &hw_acts->act_list, next) {\n \t\tuint32_t jump_group;\n+\t\tuint32_t tag;\n \t\tstruct mlx5_hw_jump_action *jump;\n \t\tstruct mlx5_hrxq *hrxq;\n \n@@ -435,6 +475,12 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_VOID:\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_MARK:\n+\t\t\ttag = mlx5_flow_mark_set\n+\t\t\t (((const struct rte_flow_action_mark *)\n+\t\t\t (action->conf))->id);\n+\t\t\trule_acts[act_data->action_dst].tag.value = tag;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_JUMP:\n \t\t\tjump_group = ((const struct rte_flow_action_jump *)\n \t\t\t\t\t\taction->conf)->group;\n@@ -1027,6 +1073,8 @@ flow_hw_table_destroy(struct rte_eth_dev *dev,\n \t\t__atomic_sub_fetch(&table->its[i]->refcnt,\n \t\t\t\t 1, __ATOMIC_RELAXED);\n \tfor (i = 0; i < table->nb_action_templates; i++) {\n+\t\tif (table->ats[i].acts.mark)\n+\t\t\tflow_hw_rxq_flag_set(dev, false);\n \t\t__flow_hw_action_template_destroy(dev, &table->ats[i].acts);\n \t\t__atomic_sub_fetch(&table->ats[i].action_template->refcnt,\n \t\t\t\t 1, __ATOMIC_RELAXED);\n@@ -1561,15 +1609,20 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\t\tif (!priv->hw_drop[i][j])\n \t\t\t\tgoto err;\n \t\t}\n+\t\tpriv->hw_tag[i] = mlx5dr_action_create_tag\n+\t\t\t(priv->dr_ctx, mlx5_hw_act_flag[i][0]);\n+\t\tif (!priv->hw_tag[i])\n+\t\t\tgoto err;\n \t}\n \treturn 0;\n err:\n \tfor (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {\n \t\tfor (j = 0; j < MLX5DR_TABLE_TYPE_MAX; j++) {\n-\t\t\tif (!priv->hw_drop[i][j])\n-\t\t\t\tcontinue;\n-\t\t\tmlx5dr_action_destroy(priv->hw_drop[i][j]);\n+\t\t\tif (priv->hw_drop[i][j])\n+\t\t\t\tmlx5dr_action_destroy(priv->hw_drop[i][j]);\n \t\t}\n+\t\tif (priv->hw_tag[i])\n+\t\t\tmlx5dr_action_destroy(priv->hw_tag[i]);\n \t}\n \tif (dr_ctx)\n \t\tclaim_zero(mlx5dr_context_close(dr_ctx));\n@@ -1615,10 +1668,11 @@ flow_hw_resource_release(struct rte_eth_dev *dev)\n \t}\n \tfor (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {\n \t\tfor (j = 0; j < MLX5DR_TABLE_TYPE_MAX; j++) {\n-\t\t\tif (!priv->hw_drop[i][j])\n-\t\t\t\tcontinue;\n-\t\t\tmlx5dr_action_destroy(priv->hw_drop[i][j]);\n+\t\t\tif (priv->hw_drop[i][j])\n+\t\t\t\tmlx5dr_action_destroy(priv->hw_drop[i][j]);\n \t\t}\n+\t\tif (priv->hw_tag[i])\n+\t\t\tmlx5dr_action_destroy(priv->hw_tag[i]);\n \t}\n \tif (priv->acts_ipool) {\n \t\tmlx5_ipool_destroy(priv->acts_ipool);\n", "prefixes": [ "v3", "12/14" ] }