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GET /api/patches/108208/?format=api
{ "id": 108208, "url": "http://patches.dpdk.org/api/patches/108208/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220224031029.14049-10-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220224031029.14049-10-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220224031029.14049-10-suanmingm@nvidia.com", "date": "2022-02-24T03:10:24", "name": "[v3,09/14] net/mlx5: add flow flush function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "59802264a6c361e98995a9cef5ecd664c7980603", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220224031029.14049-10-suanmingm@nvidia.com/mbox/", "series": [ { "id": 21839, "url": "http://patches.dpdk.org/api/series/21839/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21839", "date": "2022-02-24T03:10:16", "name": "net/mlx5: add hardware steering", "version": 3, "mbox": "http://patches.dpdk.org/series/21839/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/108208/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/108208/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 91C37A0353;\n\tThu, 24 Feb 2022 04:11:32 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DC74041181;\n\tThu, 24 Feb 2022 04:11:10 +0100 (CET)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2072.outbound.protection.outlook.com [40.107.236.72])\n by mails.dpdk.org (Postfix) with ESMTP id 23FAD41172\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH v3 09/14] net/mlx5: add flow flush function", "Date": "Thu, 24 Feb 2022 05:10:24 +0200", "Message-ID": "<20220224031029.14049-10-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220224031029.14049-1-suanmingm@nvidia.com>", "References": "<20220210162926.20436-1-suanmingm@nvidia.com>\n <20220224031029.14049-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "fb85d59c-5dcd-4a1b-30d4-08d9f7434ab1", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB4265:EE_", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB426524D1DC649DFE61D773FAC13D9@DM6PR12MB4265.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 7PV9jlfAEjIz0g32bCD6NVhk6fpvAUruFpPkfgzIwx9V/36rfD0XHAABN7Pu/0n3qJJjbF3FBQ2fAmJ2x53q7x1LRqQEBnDvn7iSASm4CAXuSPhw32nOen2nT/DcxU3/854ClRQNOAoZW04XVZIqZqcZcYU6qjMy5TM+4bQ+DL/A2/ZhneDrI+MOBL1nBisC2gSCICgLaAHb67HPHzf5mTvf64bsft/gukoAb0dVouxS+99I5pzVeUrXcRB9gIIKD4SiUp8sz5PhAt633phDAhym0ffpbBf19Ay79Ea264FoiNw/x1CiNt759NDYdVinzcUmph0o24EEOyXF+kUw+QT9QimrTcjtwYhIRjmPQmt+MjydXoUZgj3ROcNB8R9PzNncNSYWFy6ZpE1uVJuQZ4oILT5B7TOfTGniY2pKF+90AxNoXZ8SaKArErkCPOLefxFwf/9FLhHXBH+CIMC+auOo4+cXNSBBQqi36cZLu3iR9fHaZlYpACcx8+p7vAvG3q13v9nBsJYv3YMA8hxyY9Dsq8Dxyu9DKwH92Ibv8jUdIc28Q7EBOzdvsTOUBKseIC8Hb5FTc51wcIiaNmDiMNO5h+L3MZM1qAeBHhLlbZxIjdVg/qSU1/4KdhVJcoP9WXap7nYgzuaZsd3RFR6+//Vpm7FgHF7AGQ63liFhGP9cbEa/JR6ooic1L/Omc1olTVsKz+Ehx8pXu1aRUsEmWw==", "X-Forefront-Antispam-Report": "CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(356005)(6286002)(70206006)(316002)(81166007)(6636002)(54906003)(6666004)(82310400004)(4326008)(2906002)(47076005)(70586007)(110136005)(26005)(186003)(16526019)(8676002)(1076003)(2616005)(5660300002)(336012)(426003)(8936002)(86362001)(7696005)(508600001)(40460700003)(36756003)(36860700001)(55016003)(83380400001)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Feb 2022 03:11:03.6381 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n fb85d59c-5dcd-4a1b-30d4-08d9f7434ab1", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT020.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4265", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "In case port is being stopped, all created flows should be flushed.\nThis commit adds the flow flush helper function.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.c | 8 ++\n drivers/net/mlx5/mlx5_flow_hw.c | 129 ++++++++++++++++++++++++++++++++\n 2 files changed, 137 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex ad131c1b22..1672939200 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -7015,6 +7015,14 @@ mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type,\n \tuint32_t num_flushed = 0, fidx = 1;\n \tstruct rte_flow *flow;\n \n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tif (priv->sh->config.dv_flow_en == 2 &&\n+\t type == MLX5_FLOW_TYPE_GEN) {\n+\t\tflow_hw_q_flow_flush(dev, NULL);\n+\t\treturn;\n+\t}\n+#endif\n+\n \tMLX5_IPOOL_FOREACH(priv->flows[type], fidx, flow) {\n \t\tflow_list_destroy(dev, type, fidx);\n \t\tnum_flushed++;\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex accc3a96d9..ed14eacce2 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -13,6 +13,12 @@\n /* The maximum actions support in the flow. */\n #define MLX5_HW_MAX_ACTS 16\n \n+/* Default push burst threshold. */\n+#define BURST_THR 32u\n+\n+/* Default queue to flush the flows. */\n+#define MLX5_DEFAULT_FLUSH_QUEUE 0\n+\n const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops;\n \n /* DR action flags with different table. */\n@@ -391,6 +397,129 @@ flow_hw_push(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+/**\n+ * Drain the enqueued flows' completion.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[in] queue\n+ * The queue to pull the flow.\n+ * @param[in] pending_rules\n+ * The pending flow number.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, negative value otherwise and rte_errno is set.\n+ */\n+static int\n+__flow_hw_pull_comp(struct rte_eth_dev *dev,\n+\t\t uint32_t queue,\n+\t\t uint32_t pending_rules,\n+\t\t struct rte_flow_error *error)\n+{\n+\tstruct rte_flow_op_result comp[BURST_THR];\n+\tint ret, i, empty_loop = 0;\n+\n+\tflow_hw_push(dev, queue, error);\n+\twhile (pending_rules) {\n+\t\tret = flow_hw_pull(dev, queue, comp, BURST_THR, error);\n+\t\tif (ret < 0)\n+\t\t\treturn -1;\n+\t\tif (!ret) {\n+\t\t\trte_delay_us_sleep(20000);\n+\t\t\tif (++empty_loop > 5) {\n+\t\t\t\tDRV_LOG(WARNING, \"No available dequeue, quit.\");\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tcontinue;\n+\t\t}\n+\t\tfor (i = 0; i < ret; i++) {\n+\t\t\tif (comp[i].status == RTE_FLOW_OP_ERROR)\n+\t\t\t\tDRV_LOG(WARNING, \"Flow flush get error CQE.\");\n+\t\t}\n+\t\tif ((uint32_t)ret > pending_rules) {\n+\t\t\tDRV_LOG(WARNING, \"Flow flush get extra CQE.\");\n+\t\t\treturn rte_flow_error_set(error, ERANGE,\n+\t\t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t\t\"get extra CQE\");\n+\t\t}\n+\t\tpending_rules -= ret;\n+\t\tempty_loop = 0;\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * Flush created flows.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, negative value otherwise and rte_errno is set.\n+ */\n+int\n+flow_hw_q_flow_flush(struct rte_eth_dev *dev,\n+\t\t struct rte_flow_error *error)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hw_q *hw_q;\n+\tstruct rte_flow_template_table *tbl;\n+\tstruct rte_flow_hw *flow;\n+\tstruct rte_flow_op_attr attr = {\n+\t\t.postpone = 0,\n+\t};\n+\tuint32_t pending_rules = 0;\n+\tuint32_t queue;\n+\tuint32_t fidx;\n+\n+\t/*\n+\t * Ensure to push and dequeue all the enqueued flow\n+\t * creation/destruction jobs in case user forgot to\n+\t * dequeue. Or the enqueued created flows will be\n+\t * leaked. The forgotten dequeues would also cause\n+\t * flow flush get extra CQEs as expected and pending_rules\n+\t * be minus value.\n+\t */\n+\tfor (queue = 0; queue < priv->nb_queue; queue++) {\n+\t\thw_q = &priv->hw_q[queue];\n+\t\tif (__flow_hw_pull_comp(dev, queue, hw_q->size - hw_q->job_idx,\n+\t\t\t\t\terror))\n+\t\t\treturn -1;\n+\t}\n+\t/* Flush flow per-table from MLX5_DEFAULT_FLUSH_QUEUE. */\n+\thw_q = &priv->hw_q[MLX5_DEFAULT_FLUSH_QUEUE];\n+\tLIST_FOREACH(tbl, &priv->flow_hw_tbl, next) {\n+\t\tMLX5_IPOOL_FOREACH(tbl->flow, fidx, flow) {\n+\t\t\tif (flow_hw_async_flow_destroy(dev,\n+\t\t\t\t\t\tMLX5_DEFAULT_FLUSH_QUEUE,\n+\t\t\t\t\t\t&attr,\n+\t\t\t\t\t\t(struct rte_flow *)flow,\n+\t\t\t\t\t\tNULL,\n+\t\t\t\t\t\terror))\n+\t\t\t\treturn -1;\n+\t\t\tpending_rules++;\n+\t\t\t/* Drain completion with queue size. */\n+\t\t\tif (pending_rules >= hw_q->size) {\n+\t\t\t\tif (__flow_hw_pull_comp(dev,\n+\t\t\t\t\t\tMLX5_DEFAULT_FLUSH_QUEUE,\n+\t\t\t\t\t\tpending_rules, error))\n+\t\t\t\t\treturn -1;\n+\t\t\t\tpending_rules = 0;\n+\t\t\t}\n+\t\t}\n+\t}\n+\t/* Drain left completion. */\n+\tif (pending_rules &&\n+\t __flow_hw_pull_comp(dev, MLX5_DEFAULT_FLUSH_QUEUE, pending_rules,\n+\t\t\t\terror))\n+\t\treturn -1;\n+\treturn 0;\n+}\n+\n /**\n * Create flow table.\n *\n", "prefixes": [ "v3", "09/14" ] }