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GET /api/patches/107298/?format=api
{ "id": 107298, "url": "http://patches.dpdk.org/api/patches/107298/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220210162926.20436-12-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220210162926.20436-12-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220210162926.20436-12-suanmingm@nvidia.com", "date": "2022-02-10T16:29:24", "name": "[11/13] net/mlx5: add mark action", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d396639cd2405c626c98fce9b3478f89266194e2", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220210162926.20436-12-suanmingm@nvidia.com/mbox/", "series": [ { "id": 21609, "url": "http://patches.dpdk.org/api/series/21609/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=21609", "date": "2022-02-10T16:29:13", "name": "net/mlx5: add hardware steering", "version": 1, "mbox": "http://patches.dpdk.org/series/21609/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/107298/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/107298/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0A011A00BE;\n\tThu, 10 Feb 2022 17:31:52 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D805D41181;\n\tThu, 10 Feb 2022 17:31:13 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2048.outbound.protection.outlook.com [40.107.243.48])\n by mails.dpdk.org (Postfix) with ESMTP id 4C57541159\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH 11/13] net/mlx5: add mark action", "Date": "Thu, 10 Feb 2022 18:29:24 +0200", "Message-ID": "<20220210162926.20436-12-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220210162926.20436-1-suanmingm@nvidia.com>", "References": "<20220210162926.20436-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "07be1f1f-0d0d-4d92-28b7-08d9ecb2bf11", "X-MS-TrafficTypeDiagnostic": "BL0PR12MB2371:EE_", "X-Microsoft-Antispam-PRVS": "\n <BL0PR12MB2371FC90E29774902ED98252C12F9@BL0PR12MB2371.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:3968;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n uXdzwju2DiwxdRNFkwumqTaihhimTP4V9+kGPNKfbIRvVtyhrU7T3HokEGhamDlQw3kkYSd5ygHfXgCXtOfAaBSne7Zw7ZJD7IVYy+B80/xsRYmlwnLv0fiI7ZvYlswQkXyGTgZx4yu4JWYgEA4ylFgXNMAnt3KZtkFJCNvRRfx5rpBPn2RkoJhsa7g24j4RJPXJOKzB0tM9x4RVPCm64lx8+eCzCCkazeTXMC2G8rGUKfQZuwdh7vJH3huSSqEGvP1ZBpaMTDqO7LUXiyuxQ8exYDd78kkacKUCnlMUATA4FF+JhID4prif5o613gwkDJdkf1s9lweL5Ua36TCoQ8Z0rMeNyD5Anifp6zuJtHCCJwau3L91Mag1uX9wBDEh74yrapH6vk7O3YYaLu3MEtK8RPIdpBX+jeyzZKg1maA+qZAvYCOUAJltpv4TGUP/mOF1gjC5m4txvqAswsDP5vzcOa2h4EmlDG1zLAV2Zn0e7TXNIuBC6S+4eIr6Vgx6dNM/AVNKpu5cXETSYWztCqQRoW++bjCn4wR0LlmxIOdzFN2BUOlgUF6vl9xUJkUizO3C/RVIJeJpTLJT/SfQyQE03yR6u0HLBhcuClkgckRT2Oh/XoktiUZK40gxF1corFMcKmgW+8ifxrUI290AmD88d+9hbEf550dfQCpYqWdhZR03SgceB+3+3Ha6Ga9gb4q+dvn+j1z1YmDOKAICfA==", "X-Forefront-Antispam-Report": "CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(2616005)(83380400001)(5660300002)(508600001)(6286002)(426003)(16526019)(336012)(26005)(186003)(8936002)(1076003)(82310400004)(7696005)(81166007)(6666004)(356005)(47076005)(2906002)(36860700001)(54906003)(110136005)(316002)(86362001)(6636002)(8676002)(4326008)(55016003)(36756003)(70206006)(70586007)(40460700003)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "10 Feb 2022 16:31:10.2292 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 07be1f1f-0d0d-4d92-28b7-08d9ecb2bf11", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT052.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL0PR12MB2371", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The mark action is covered by tag action internally. While it is added\nthe HW will add a tag to the packet. The mark value can be set as fixed\nor dynamic as the action mask indicates.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 3 ++\n drivers/net/mlx5/mlx5_flow.h | 1 +\n drivers/net/mlx5/mlx5_flow_hw.c | 87 ++++++++++++++++++++++++++++++---\n 3 files changed, 85 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 6fb82bf1f3..c78dc3c431 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1529,6 +1529,9 @@ struct mlx5_priv {\n \t/* HW steering global drop action. */\n \tstruct mlx5dr_action *hw_drop[MLX5_HW_ACTION_FLAG_MAX]\n \t\t\t\t [MLX5DR_TABLE_TYPE_MAX];\n+\t/* HW steering global drop action. */\n+\tstruct mlx5dr_action *hw_tag[MLX5_HW_ACTION_FLAG_MAX]\n+\t\t\t\t [MLX5DR_TABLE_TYPE_MAX];\n \tstruct mlx5_indexed_pool *acts_ipool; /* Action data indexed pool. */\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 33094c8c07..8e65486a1f 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1080,6 +1080,7 @@ struct mlx5_hw_actions {\n \tstruct mlx5_hw_jump_action *jump; /* Jump action. */\n \tstruct mlx5_hrxq *tir; /* TIR action. */\n \tuint32_t acts_num:4; /* Total action number. */\n+\tuint32_t mark:1; /* Indicate the mark action. */\n \t/* Translated DR action array from action template. */\n \tstruct mlx5dr_rule_action rule_acts[MLX5_HW_MAX_ACTS];\n };\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex e59d812072..a754cdd084 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -31,6 +31,50 @@ static uint32_t mlx5_hw_act_flag[MLX5_HW_ACTION_FLAG_MAX]\n \t},\n };\n \n+/**\n+ * Trim rxq flag refcnt.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ */\n+static void\n+flow_hw_rxq_flag_trim(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tunsigned int i;\n+\n+\tif (!priv->mark_enabled)\n+\t\treturn;\n+\tfor (i = 0; i < priv->rxqs_n; ++i) {\n+\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i);\n+\n+\t\trxq_ctrl->rxq.mark = 0;\n+\t}\n+\tpriv->mark_enabled = 0;\n+}\n+\n+/**\n+ * Set rxq flag refcnt.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ */\n+static void\n+flow_hw_rxq_flag_set(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tunsigned int i;\n+\n+\tif (priv->mark_enabled)\n+\t\treturn;\n+\tfor (i = 0; i < priv->rxqs_n; ++i) {\n+\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i);\n+\n+\t\trxq_ctrl->rxq.mark = 1;\n+\t}\n+\tpriv->mark_enabled = 1;\n+}\n+\n /**\n * Register destination table DR jump action.\n *\n@@ -292,6 +336,20 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\tacts->rule_acts[i++].action =\n \t\t\t\tpriv->hw_drop[!!attr->group][type];\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_MARK:\n+\t\t\tacts->mark = true;\n+\t\t\tif (masks->conf)\n+\t\t\t\tacts->rule_acts[i].tag.value =\n+\t\t\t\t\tmlx5_flow_mark_set\n+\t\t\t\t\t(((const struct rte_flow_action_mark *)\n+\t\t\t\t\t(masks->conf))->id);\n+\t\t\telse if (__flow_hw_act_data_general_append(priv, acts,\n+\t\t\t\tactions->type, actions - action_start, i))\n+\t\t\t\tgoto err;\n+\t\t\tacts->rule_acts[i++].action =\n+\t\t\t\tpriv->hw_tag[!!attr->group][type];\n+\t\t\tflow_hw_rxq_flag_set(dev);\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_JUMP:\n \t\t\tif (masks->conf) {\n \t\t\t\tuint32_t jump_group =\n@@ -418,6 +476,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t}\n \tLIST_FOREACH(act_data, &hw_acts->act_list, next) {\n \t\tuint32_t jump_group;\n+\t\tuint32_t tag;\n \t\tstruct mlx5_hw_jump_action *jump;\n \t\tstruct mlx5_hrxq *hrxq;\n \n@@ -429,6 +488,12 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_VOID:\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ACTION_TYPE_MARK:\n+\t\t\ttag = mlx5_flow_mark_set\n+\t\t\t (((const struct rte_flow_action_mark *)\n+\t\t\t (action->conf))->id);\n+\t\t\trule_acts[act_data->action_dst].tag.value = tag;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_JUMP:\n \t\t\tjump_group = ((const struct rte_flow_action_jump *)\n \t\t\t\t\t\taction->conf)->group;\n@@ -998,6 +1063,8 @@ flow_hw_table_destroy(struct rte_eth_dev *dev,\n \t\t__atomic_sub_fetch(&table->its[i]->refcnt,\n \t\t\t\t 1, __ATOMIC_RELAXED);\n \tfor (i = 0; i < table->nb_action_templates; i++) {\n+\t\tif (table->ats[i].acts.mark)\n+\t\t\tflow_hw_rxq_flag_trim(dev);\n \t\t__flow_hw_action_template_destroy(dev, &table->ats[i].acts);\n \t\t__atomic_sub_fetch(&table->ats[i].action_template->refcnt,\n \t\t\t\t 1, __ATOMIC_RELAXED);\n@@ -1499,15 +1566,21 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\t\t\t(priv->dr_ctx, mlx5_hw_act_flag[i][j]);\n \t\t\tif (!priv->hw_drop[i][j])\n \t\t\t\tgoto err;\n+\t\t\tpriv->hw_tag[i][j] = mlx5dr_action_create_tag\n+\t\t\t\t(priv->dr_ctx, mlx5_hw_act_flag[i][j]);\n+\t\t\tif (!priv->hw_tag[i][j])\n+\t\t\t\tgoto err;\n \t\t}\n \t}\n \treturn 0;\n err:\n \tfor (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {\n \t\tfor (j = 0; j < MLX5DR_TABLE_TYPE_MAX; j++) {\n-\t\t\tif (!priv->hw_drop[i][j])\n-\t\t\t\tcontinue;\n-\t\t\tmlx5dr_action_destroy(priv->hw_drop[i][j]);\n+\t\t\tif (priv->hw_drop[i][j])\n+\t\t\t\tmlx5dr_action_destroy(priv->hw_drop[i][j]);\n+\t\t\tif (priv->hw_tag[i][j])\n+\t\t\t\tmlx5dr_action_destroy(priv->hw_tag[i][j]);\n+\n \t\t}\n \t}\n \tif (dr_ctx)\n@@ -1556,9 +1629,11 @@ flow_hw_resource_release(struct rte_eth_dev *dev)\n \t}\n \tfor (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {\n \t\tfor (j = 0; j < MLX5DR_TABLE_TYPE_MAX; j++) {\n-\t\t\tif (!priv->hw_drop[i][j])\n-\t\t\t\tcontinue;\n-\t\t\tmlx5dr_action_destroy(priv->hw_drop[i][j]);\n+\t\t\tif (priv->hw_drop[i][j])\n+\t\t\t\tmlx5dr_action_destroy(priv->hw_drop[i][j]);\n+\t\t\tif (priv->hw_tag[i][j])\n+\t\t\t\tmlx5dr_action_destroy(priv->hw_tag[i][j]);\n+\n \t\t}\n \t}\n \tif (priv->acts_ipool) {\n", "prefixes": [ "11/13" ] }