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GET /api/patches/106952/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 106952,
    "url": "http://patches.dpdk.org/api/patches/106952/?format=api",
    "web_url": "http://patches.dpdk.org/project/dts/patch/20220207161342.94286-1-qi.fu@intel.com/",
    "project": {
        "id": 3,
        "url": "http://patches.dpdk.org/api/projects/3/?format=api",
        "name": "DTS",
        "link_name": "dts",
        "list_id": "dts.dpdk.org",
        "list_email": "dts@dpdk.org",
        "web_url": "",
        "scm_url": "git://dpdk.org/tools/dts",
        "webscm_url": "http://git.dpdk.org/tools/dts/",
        "list_archive_url": "https://inbox.dpdk.org/dts",
        "list_archive_url_format": "https://inbox.dpdk.org/dts/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220207161342.94286-1-qi.fu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dts/20220207161342.94286-1-qi.fu@intel.com",
    "date": "2022-02-07T16:13:42",
    "name": "[V4] test_plans: add test plan for cvl 1pps signal",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "dca7e40d59b58ac1181a0436d7199abec4096197",
    "submitter": {
        "id": 1689,
        "url": "http://patches.dpdk.org/api/people/1689/?format=api",
        "name": "Fu, Qi",
        "email": "qi.fu@intel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dts/patch/20220207161342.94286-1-qi.fu@intel.com/mbox/",
    "series": [
        {
            "id": 21484,
            "url": "http://patches.dpdk.org/api/series/21484/?format=api",
            "web_url": "http://patches.dpdk.org/project/dts/list/?series=21484",
            "date": "2022-02-07T16:13:42",
            "name": "[V4] test_plans: add test plan for cvl 1pps signal",
            "version": 4,
            "mbox": "http://patches.dpdk.org/series/21484/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/106952/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/106952/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dts-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D16C7A034F;\n\tMon,  7 Feb 2022 08:39:11 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 92A3D40685;\n\tMon,  7 Feb 2022 08:39:11 +0100 (CET)",
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            "from orsmga001.jf.intel.com ([10.7.209.18])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 06 Feb 2022 23:39:09 -0800",
            "from dpdk-qifu-cxl.sh.intel.com ([10.67.119.122])\n by orsmga001.jf.intel.com with ESMTP; 06 Feb 2022 23:39:07 -0800"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1644219550; x=1675755550;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=zHvj3KjdlsqeydEI3Pdwg9yI31ZMMRIrflee8H/vi5o=;\n b=TPN/izI3aOMyaFheC1g08qAmsvpIYcL2HlkVO9OeS9qRa7r/VSVeJR1+\n my/5ve/9+7RS0lbnSDiN/M3lski5q8YVbhgFMEFY1PoMm7jHBFt/NiJvC\n stST+9pMFrzyHl34a1gSkVJISJf73DJz3H8diFz4dwIIMRb1m36j6hZHL\n r1ZeFdJZJoVC98rkj2OA11GVGb9v/bpYEl9a2UpN0ds/eXHJx5kDQpYim\n KUwf9FSyE3tj/nXJyw/j1cbBtk34WxgHV60rH6INdxsKpN+avz6W9L9kq\n jbBtAI2jF1dOoLl/5BottmbOwoqzO7Z8b3XNU/aMm4pqF7sZwHfb9AbzF Q==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,10250\"; a=\"311960878\"",
            "E=Sophos;i=\"5.88,349,1635231600\"; d=\"scan'208\";a=\"311960878\"",
            "E=Sophos;i=\"5.88,349,1635231600\"; d=\"scan'208\";a=\"567390091\""
        ],
        "X-ExtLoop1": "1",
        "From": "Qi Fu <qi.fu@intel.com>",
        "To": "dts@dpdk.org",
        "Cc": "Qi Fu <qi.fu@intel.com>",
        "Subject": "[dts][PATCH V4]test_plans: add test plan for cvl 1pps signal",
        "Date": "Tue,  8 Feb 2022 00:13:42 +0800",
        "Message-Id": "<20220207161342.94286-1-qi.fu@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "quoted-printable",
        "X-BeenThere": "dts@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "test suite reviews and discussions <dts.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dts>,\n <mailto:dts-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dts/>",
        "List-Post": "<mailto:dts@dpdk.org>",
        "List-Help": "<mailto:dts-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dts>,\n <mailto:dts-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dts-bounces@dpdk.org"
    },
    "content": "Add test plan for cvl enable 1PPS signal.\n\nSigned-off-by: Qi Fu <qi.fu@intel.com>\n---\n test_plans/cvl_1pps_signal_test_plan.rst | 160 +++++++++++++++++++++++\n test_plans/index.rst                     |   1 +\n 2 files changed, 161 insertions(+)\n create mode 100644 test_plans/cvl_1pps_signal_test_plan.rst",
    "diff": "diff --git a/test_plans/cvl_1pps_signal_test_plan.rst b/test_plans/cvl_1pps_signal_test_plan.rst\nnew file mode 100644\nindex 00000000..8d279ff7\n--- /dev/null\n+++ b/test_plans/cvl_1pps_signal_test_plan.rst\n@@ -0,0 +1,160 @@\n+.. Copyright (c) <2021>, Intel Corporation\r\n+   All rights reserved.\r\n+\r\n+   Redistribution and use in source and binary forms, with or without\r\n+   modification, are permitted provided that the following conditions\r\n+   are met:\r\n+\r\n+   - Redistributions of source code must retain the above copyright\r\n+     notice, this list of conditions and the following disclaimer.\r\n+\r\n+   - Redistributions in binary form must reproduce the above copyright\r\n+     notice, this list of conditions and the following disclaimer in\r\n+     the documentation and/or other materials provided with the\r\n+     distribution.\r\n+\r\n+   - Neither the name of Intel Corporation nor the names of its\r\n+     contributors may be used to endorse or promote products derived\r\n+     from this software without specific prior written permission.\r\n+\r\n+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r\n+   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r\n+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r\n+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r\n+   COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r\n+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r\n+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r\n+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r\n+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r\n+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\r\n+   OF THE POSSIBILITY OF SUCH DAMAGE.\r\n+\r\n+=========================\r\n+CVL 1PPS Signal Test Plan\r\n+=========================\r\n+\r\n+Description\r\n+===========\r\n+The E810 supports a total of four single-ended GPIO signals(SPD[20:23])plus one different GPIO signal (CLK_OUT_P/N),\r\n+which is configured by default 1PPS(out). The SPD[20:23] is mapping to pin_id[0:3].\r\n+This test plan is designed to check the value of related registers, which make up the 1PPS signal.\r\n+The registers address depends on some hardware config.\r\n+The test cases only give the example of Columbiaville_25g and Columbiaville_100g.\r\n+\r\n+\r\n+Prerequisites\r\n+=============\r\n+\r\n+Topology\r\n+--------\r\n+DUT port 0 <----> Tester port 0\r\n+\r\n+Hardware\r\n+--------\r\n+Supported NICs: columbiaville_25g/columbiaville_100g\r\n+\r\n+Software\r\n+--------\r\n+dpdk: http://dpdk.org/git/dpdk\r\n+scapy: http://www.secdev.org/projects/scapy/\r\n+\r\n+General set up\r\n+--------------\r\n+1. Compile DPDK::\r\n+\r\n+    # CC=gcc meson --werror -Denable_kmods=True -Dlibdir=lib --default-library=static <dpdk build dir>\r\n+    # ninja -C <dpdk build dir> -j 110\r\n+\r\n+2. Get the pci device id and interface of DUT and tester.\r\n+   For example, 0000:18:00.0 and 0000:18:00.1 is pci device id,\r\n+   ens785f0 and ens785f1 is interface::\r\n+\r\n+    <dpdk dir># ./usertools/dpdk-devbind.py -s\r\n+\r\n+    0000:18:00.0 'Device 159b' if=ens785f0 drv=ice unused=vfio-pci\r\n+    0000:18:00.1 'Device 159b' if=ens785f1 drv=ice unused=vfio-pci\r\n+\r\n+3. Bind the DUT port to dpdk::\r\n+\r\n+    <dpdk dir># ./usertools/dpdk-devbind.py -b vfio-pci <DUT port pci device id>\r\n+\r\n+\r\n+Test case\r\n+=========\r\n+\r\n+Test case 1: check registers when pin id is 0\r\n+---------------------------------------------\r\n+\r\n+this case is designed to check the register value is right when pin id is 0.\r\n+\r\n+test steps\r\n+~~~~~~~~~~\r\n+1. start testpmd with different pin_id and dump registers::\r\n+\r\n+    <dpdk build dir>/app/dpdk-testpmd <EAL options> -a <DUT port pci device id>,pps_out='[pin:0]' -- -i --rxq=4 --txq=4\r\n+    testpmd> read reg 0 0x00088998\r\n+    testpmd> read reg 0 0x000889B8\r\n+    testpmd> read reg 0 0x00088928\r\n+    testpmd> read reg 0 0x00088930\r\n+    testpmd> read reg 0 0x000880C8\r\n+\r\n+2. check the GLTSYN_AUX_OUT_0[0] 0x00088998 is 0x00000007 (7), GLTSYN_CLKO_0[0] 0x000889B8 is 0x1DCD6500 (500000000), the 0x00088928 and 0x00088930 is non-zero,\r\n+   The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[0] 0x000880C8 is 8. And the 4th binary digit is 1.\r\n+\r\n+Test case 2: check registers when pin id is 1\r\n+---------------------------------------------\r\n+\r\n+this case is designed to check the register value is right when pin id is 1.\r\n+\r\n+test steps\r\n+~~~~~~~~~~\r\n+1. start testpmd with different pin_id and dump registers::\r\n+\r\n+    ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:00.0,pps_out='[pin:1]' -- -i --rxq=4 --txq=4\r\n+    testpmd> read reg 0 0x000889A0\r\n+    testpmd> read reg 0 0x000889C0\r\n+    testpmd> read reg 0 0x00088938\r\n+    testpmd> read reg 0 0x00088940\r\n+    testpmd> read reg 0 0x000880CC\r\n+\r\n+2. check the GLTSYN_AUX_OUT_1[0] 0x000889A0 is 0x00000007 (7), GLTSYN_CLKO_1[0] 0x000889C0 is 0x1DCD6500 (500000000), the 0x00088938 and 0x00088940 is non-zero,\r\n+   The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[1] 0x000880CC is 9. And the 4th binary digit is 1.\r\n+\r\n+Test case 3: check registers when pin id is 2\r\n+---------------------------------------------\r\n+\r\n+this case is designed to check the register value is right when pin id is 2.\r\n+\r\n+test steps\r\n+~~~~~~~~~~\r\n+1. start testpmd with different pin_id and dump registers::\r\n+\r\n+    ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:00.0,pps_out='[pin:2]' -- -i --rxq=4 --txq=4\r\n+    testpmd> read reg 0 0x000889A8\r\n+    testpmd> read reg 0 0x000889C8\r\n+    testpmd> read reg 0 0x00088948\r\n+    testpmd> read reg 0 0x00088950\r\n+    testpmd> read reg 0 0x000880D0\r\n+\r\n+2. check the GLTSYN_AUX_OUT_2[0] 0x000889A8 is 0x00000007 (7), GLTSYN_CLKO_2[0] 0x000889C8 is 0x1DCD6500 (500000000), the 0x00088948 and 0x00088950 is non-zero,\r\n+   The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[2] 0x000880D0 is A. And the 4th binary digit is 1.\r\n+\r\n+Test case 4: check registers when pin id is 3\r\n+---------------------------------------------\r\n+\r\n+this case is designed to check the register value is right when pin id is 3.\r\n+\r\n+test steps\r\n+~~~~~~~~~~\r\n+1. start testpmd with different pin_id and dump registers::\r\n+\r\n+    ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:00.0,pps_out='[pin:3]' -- -i --rxq=4 --txq=4\r\n+    testpmd> read reg 0 0x000889B0\r\n+    testpmd> read reg 0 0x000889D0\r\n+    testpmd> read reg 0 0x00088958\r\n+    testpmd> read reg 0 0x00088960\r\n+    testpmd> read reg 0 0x000880D4\r\n+\r\n+2. check the GLTSYN_AUX_OUT_3[0] 0x000889B0 is 0x00000007 (7), GLTSYN_CLKO_3[0] 0x000889D0 is 0x1DCD6500 (500000000), the 0x00088958 and 0x00088960 is non-zero,\r\n+   The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[3] 0x000880D4 is B. And the 4th binary digit is 1.\n\\ No newline at end of file\ndiff --git a/test_plans/index.rst b/test_plans/index.rst\nindex 68250fca..f83bacfe 100644\n--- a/test_plans/index.rst\n+++ b/test_plans/index.rst\n@@ -69,6 +69,7 @@ The following are the test plans for the DPDK DTS automated test system.\n     cvl_switch_filter_test_plan\n     cvl_switch_filter_pppoe_test_plan\n     cvl_vf_support_multicast_address_test_plan\n+    cvl_1pps_signal_test_plan\n     cloud_filter_with_l4_port_test_plan\n     dcf_lifecycle_test_plan\n     crypto_perf_cryptodev_perf_test_plan\n",
    "prefixes": [
        "V4"
    ]
}