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GET /api/patches/105282/?format=api
{ "id": 105282, "url": "http://patches.dpdk.org/api/patches/105282/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211220102710.3083370-3-g.singh@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211220102710.3083370-3-g.singh@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211220102710.3083370-3-g.singh@nxp.com", "date": "2021-12-20T10:27:05", "name": "[3/8] crypto/dpaa2_sec: ordered queue support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8c1c8db2bd7c019fd1a8ab99c7ad189e6f1432b3", "submitter": { "id": 1068, "url": "http://patches.dpdk.org/api/people/1068/?format=api", "name": "Gagandeep Singh", "email": "g.singh@nxp.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211220102710.3083370-3-g.singh@nxp.com/mbox/", "series": [ { "id": 20982, "url": "http://patches.dpdk.org/api/series/20982/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20982", "date": "2021-12-20T10:27:04", "name": "[1/8] common/dpaax: caamflib: Remove code related to SEC ERA 1 to 7", "version": 1, "mbox": "http://patches.dpdk.org/series/20982/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105282/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/105282/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D9EA2A00BE;\n\tMon, 20 Dec 2021 11:27:58 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 90C9341143;\n\tMon, 20 Dec 2021 11:27:47 +0100 (CET)", "from EUR02-AM5-obe.outbound.protection.outlook.com\n (mail-eopbgr00074.outbound.protection.outlook.com [40.107.0.74])\n by mails.dpdk.org (Postfix) with ESMTP id 7888E4067C\n for <dev@dpdk.org>; Mon, 20 Dec 2021 11:27:45 +0100 (CET)", "from AS8PR04MB8198.eurprd04.prod.outlook.com (2603:10a6:20b:3b0::14)\n by AM6PR0402MB3703.eurprd04.prod.outlook.com (2603:10a6:209:19::30)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4801.20; Mon, 20 Dec\n 2021 10:27:43 +0000", "from AS8PR04MB8198.eurprd04.prod.outlook.com\n ([fe80::71ab:27ce:856d:5aac]) by AS8PR04MB8198.eurprd04.prod.outlook.com\n ([fe80::71ab:27ce:856d:5aac%4]) with mapi id 15.20.4801.020; Mon, 20 Dec 2021\n 10:27:43 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=Nz8IM6nSP+3hq4Og/pauP+bnFVa3qqcBd/4X1yAGXzxqYTgfgTmtwiFyP4/cALQ0UHBTwyVOF1dWICoUIA8hXJ3v3Rzlc9YkC036vPJ8D1gAMsnZgPbRmeok5SbNh0NUqTvFHcMlyltxAjo0M/DjoEBQeM0FcMY28lALHIT3fW7ylLcGpAM3+8ijP/6oYENqifgXo2gORC5McDRgoTgM+VPryuNReHfTuE8ZtPsrPlWaccUeW7tS9Yi6DMZFAFLuaVb3+zfZ5f7p3MH+JSHiep3hlTRmWs6ur92gu/61fY6z1mfF4m6wJsJMpCTXb7A4MGLuE2bSha2oDL+pZRUvcQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=lDjWAy47x5cY8icoRld4jLPDQey9Vg9RQMCZ5uSIl+M=;\n b=LyYMf7LSfHwmrmvexs517kDC1DhSZOB1CYzScePDcOihNj4k5VoRAa6dVkSfQX1521HcrIObzitKzmhNWpM6k13wdY+Hvq+VfuvbcVVw6nDmIhWZuWm8n9qVSC+Nnea4IfLEH8la0uMaON+smwm2UT+Ye1jZZO+M2SH8+ScXX4HZx2jL3xYHX84aGz5PhDgo6qbeB//R799nRv0HGDrBwSIc561IiDWO9hh9p4f/kJ7HhcRYjBvr5pDN1CU1eB4UAvv+8dIHcFybCRYgdwilXlOruKbVNmJ4GnW95KtBN8a0vjZVFVH3oKcUb/Qh8TAzaqbGkWOztNI206f3EII75w==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass\n header.d=nxp.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=lDjWAy47x5cY8icoRld4jLPDQey9Vg9RQMCZ5uSIl+M=;\n b=DByvM25xeyYicUZFPTQYVaCgBqgBwiwjrqBDSQ/A+iixBqZ4qt00Cg1xs7f3uetNT5I0M0TxmL5omfn/2m8kcsRu5AaqLJH/viWTmVPsTDxVnkrcPaNb7fG0NoWPJqVFWcZBRHAC/9Rhz54BHHT2NTjjBbNSWpjIOEdQ+TipdEY=", "Authentication-Results": "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nxp.com;", "From": "Gagandeep Singh <g.singh@nxp.com>", "To": "gakhil@marvell.com,\n\tdev@dpdk.org", "Cc": "Nipun Gupta <nipun.gupta@nxp.com>", "Subject": "[PATCH 3/8] crypto/dpaa2_sec: ordered queue support", "Date": "Mon, 20 Dec 2021 15:57:05 +0530", "Message-Id": "<20211220102710.3083370-3-g.singh@nxp.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211220102710.3083370-1-g.singh@nxp.com>", "References": "<20211220102710.3083370-1-g.singh@nxp.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SG2PR06CA0205.apcprd06.prod.outlook.com\n (2603:1096:4:68::13) To AS8PR04MB8198.eurprd04.prod.outlook.com\n (2603:10a6:20b:3b0::14)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "2873c474-b176-4a61-b837-08d9c3a35b5d", "X-MS-TrafficTypeDiagnostic": "AM6PR0402MB3703:EE_", "X-Microsoft-Antispam-PRVS": "\n <AM6PR0402MB3703C26FE491B8550CFB90CBE17B9@AM6PR0402MB3703.eurprd04.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:7219;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Zyhv1CCgCeShfyvpuHajAXTZouToKth7C0iywczgMjQqPCMqYBC0PO7WRS22u4SC8IpCCDrCc1SBa+5JgWn54EVwOZLEtOhXumRYdq9WJxwrol1nj+i+QfxdS0ewEdAbB/EuGD/c6hIqieiTgG/wZw1+equojvBiMU0HsyEm9jGiu+AE9bAzPlvvJL809jHWv3TleFt3Gn+nYRbJnHjv9EhQ6lbQAR0xIMo+5QvHQeCYP1wGYEvogzm5AflBsJQfzBO8ylQ4C0tpMqPLooklz8kNTL3hAAWgeg9pOh0dcT+GcU5l8+KcCvC4WVwbbJdF30q890BjlnjIHDSLK4vJWTq0AFoGhIzoePy5VEihqjdkM1+4etjng1l9zbkd8Zi4EJSS+v/J9bkpSxEaaWMnFltM0BrrOygYoG3dH0fhgcbGGmJDMVlFbEIcTRpstqPB7YAqwN7O9LFQ29bpuzv9Q3QqhJEhEWRNGFwhDhPFxuIduUDKkxtntFW5hxXL0LDePFl7YGk+BdcoJ0fgvCqEc7IbDYdxGGG7oqaDjCG+WviR5onKqj8EyMEuMKSo+U9hDALlmwBu8CA9jIsvo9H/5F6/m485YaVcRH/Q/Egv/HS1f0yyap0WCPwFbo4VqtIFEZQH9WL3CliRD8ar8Dw5vbkNYmRDQFxMPvBI1O/OA/lgMvRfc0XfFcTE2pU/DLP00uLIWYoLrgvkfQaw/Xr0yg==", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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loop < frames_to_send; loop++) {\n \t\t\tif (*dpaa2_seqn((*ops)->sym->m_src)) {\n-\t\t\t\tuint8_t dqrr_index =\n-\t\t\t\t\t*dpaa2_seqn((*ops)->sym->m_src) - 1;\n-\n-\t\t\t\tflags[loop] = QBMAN_ENQUEUE_FLAG_DCA | dqrr_index;\n-\t\t\t\tDPAA2_PER_LCORE_DQRR_SIZE--;\n-\t\t\t\tDPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);\n-\t\t\t\t*dpaa2_seqn((*ops)->sym->m_src) =\n-\t\t\t\t\tDPAA2_INVALID_MBUF_SEQN;\n+\t\t\t\tif (*dpaa2_seqn((*ops)->sym->m_src) & QBMAN_ENQUEUE_FLAG_DCA) {\n+\t\t\t\t\tDPAA2_PER_LCORE_DQRR_SIZE--;\n+\t\t\t\t\tDPAA2_PER_LCORE_DQRR_HELD &= ~(1 <<\n+\t\t\t\t\t*dpaa2_seqn((*ops)->sym->m_src) &\n+\t\t\t\t\tQBMAN_EQCR_DCA_IDXMASK);\n+\t\t\t\t}\n+\t\t\t\tflags[loop] = *dpaa2_seqn((*ops)->sym->m_src);\n+\t\t\t\t*dpaa2_seqn((*ops)->sym->m_src) = DPAA2_INVALID_MBUF_SEQN;\n \t\t\t}\n \n \t\t\t/*Clear the unused FD fields before sending*/\n@@ -1621,6 +1621,169 @@ sec_fd_to_mbuf(const struct qbman_fd *fd)\n \treturn op;\n }\n \n+static void\n+dpaa2_sec_free_eqresp_buf(uint16_t eqresp_ci)\n+{\n+\tstruct dpaa2_dpio_dev *dpio_dev = DPAA2_PER_LCORE_DPIO;\n+\tstruct rte_crypto_op *op;\n+\tstruct qbman_fd *fd;\n+\n+\tfd = qbman_result_eqresp_fd(&dpio_dev->eqresp[eqresp_ci]);\n+\top = sec_fd_to_mbuf(fd);\n+\t/* Instead of freeing, enqueue it to the sec tx queue (sec->core)\n+\t * after setting an error in FD. But this will have performance impact.\n+\t */\n+\trte_pktmbuf_free(op->sym->m_src);\n+}\n+\n+static void\n+dpaa2_sec_set_enqueue_descriptor(struct dpaa2_queue *dpaa2_q,\n+\t\t\t struct rte_mbuf *m,\n+\t\t\t struct qbman_eq_desc *eqdesc)\n+{\n+\tstruct dpaa2_dpio_dev *dpio_dev = DPAA2_PER_LCORE_DPIO;\n+\tstruct eqresp_metadata *eqresp_meta;\n+\tstruct dpaa2_sec_dev_private *priv = dpaa2_q->crypto_data->dev_private;\n+\tuint16_t orpid, seqnum;\n+\tuint8_t dq_idx;\n+\n+\tif (*dpaa2_seqn(m) & DPAA2_ENQUEUE_FLAG_ORP) {\n+\t\torpid = (*dpaa2_seqn(m) & DPAA2_EQCR_OPRID_MASK) >>\n+\t\t\tDPAA2_EQCR_OPRID_SHIFT;\n+\t\tseqnum = (*dpaa2_seqn(m) & DPAA2_EQCR_SEQNUM_MASK) >>\n+\t\t\tDPAA2_EQCR_SEQNUM_SHIFT;\n+\n+\n+\t\tif (!priv->en_loose_ordered) {\n+\t\t\tqbman_eq_desc_set_orp(eqdesc, 1, orpid, seqnum, 0);\n+\t\t\tqbman_eq_desc_set_response(eqdesc, (uint64_t)\n+\t\t\t\tDPAA2_VADDR_TO_IOVA(&dpio_dev->eqresp[\n+\t\t\t\tdpio_dev->eqresp_pi]), 1);\n+\t\t\tqbman_eq_desc_set_token(eqdesc, 1);\n+\n+\t\t\teqresp_meta = &dpio_dev->eqresp_meta[dpio_dev->eqresp_pi];\n+\t\t\teqresp_meta->dpaa2_q = dpaa2_q;\n+\t\t\teqresp_meta->mp = m->pool;\n+\n+\t\t\tdpio_dev->eqresp_pi + 1 < MAX_EQ_RESP_ENTRIES ?\n+\t\t\t\tdpio_dev->eqresp_pi++ : (dpio_dev->eqresp_pi = 0);\n+\t\t} else {\n+\t\t\tqbman_eq_desc_set_orp(eqdesc, 0, orpid, seqnum, 0);\n+\t\t}\n+\t} else {\n+\t\tdq_idx = *dpaa2_seqn(m) - 1;\n+\t\tqbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0);\n+\t\tDPAA2_PER_LCORE_DQRR_SIZE--;\n+\t\tDPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dq_idx);\n+\t}\n+\t*dpaa2_seqn(m) = DPAA2_INVALID_MBUF_SEQN;\n+}\n+\n+\n+static uint16_t\n+dpaa2_sec_enqueue_burst_ordered(void *qp, struct rte_crypto_op **ops,\n+\t\t\tuint16_t nb_ops)\n+{\n+\t/* Function to transmit the frames to given device and VQ*/\n+\tuint32_t loop;\n+\tint32_t ret;\n+\tstruct qbman_fd fd_arr[MAX_TX_RING_SLOTS];\n+\tuint32_t frames_to_send, num_free_eq_desc, retry_count;\n+\tstruct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS];\n+\tstruct dpaa2_sec_qp *dpaa2_qp = (struct dpaa2_sec_qp *)qp;\n+\tstruct qbman_swp *swp;\n+\tuint16_t num_tx = 0;\n+\t/*todo - need to support multiple buffer pools */\n+\tuint16_t bpid;\n+\tstruct rte_mempool *mb_pool;\n+\tstruct dpaa2_sec_dev_private *priv =\n+\t\t\t\tdpaa2_qp->tx_vq.crypto_data->dev_private;\n+\n+\tif (unlikely(nb_ops == 0))\n+\t\treturn 0;\n+\n+\tif (ops[0]->sess_type == RTE_CRYPTO_OP_SESSIONLESS) {\n+\t\tDPAA2_SEC_ERR(\"sessionless crypto op not supported\");\n+\t\treturn 0;\n+\t}\n+\n+\tif (!DPAA2_PER_LCORE_DPIO) {\n+\t\tret = dpaa2_affine_qbman_swp();\n+\t\tif (ret) {\n+\t\t\tDPAA2_SEC_ERR(\"Failure in affining portal\");\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\tswp = DPAA2_PER_LCORE_PORTAL;\n+\n+\twhile (nb_ops) {\n+\t\tframes_to_send = (nb_ops > dpaa2_eqcr_size) ?\n+\t\t\tdpaa2_eqcr_size : nb_ops;\n+\n+\t\tif (!priv->en_loose_ordered) {\n+\t\t\tif (*dpaa2_seqn((*ops)->sym->m_src)) {\n+\t\t\t\tnum_free_eq_desc = dpaa2_free_eq_descriptors();\n+\t\t\t\tif (num_free_eq_desc < frames_to_send)\n+\t\t\t\t\tframes_to_send = num_free_eq_desc;\n+\t\t\t}\n+\t\t}\n+\n+\t\tfor (loop = 0; loop < frames_to_send; loop++) {\n+\t\t\t/*Prepare enqueue descriptor*/\n+\t\t\tqbman_eq_desc_clear(&eqdesc[loop]);\n+\t\t\tqbman_eq_desc_set_fq(&eqdesc[loop], dpaa2_qp->tx_vq.fqid);\n+\n+\t\t\tif (*dpaa2_seqn((*ops)->sym->m_src))\n+\t\t\t\tdpaa2_sec_set_enqueue_descriptor(\n+\t\t\t\t\t\t&dpaa2_qp->tx_vq,\n+\t\t\t\t\t\t(*ops)->sym->m_src,\n+\t\t\t\t\t\t&eqdesc[loop]);\n+\t\t\telse\n+\t\t\t\tqbman_eq_desc_set_no_orp(&eqdesc[loop],\n+\t\t\t\t\t\t\t DPAA2_EQ_RESP_ERR_FQ);\n+\n+\t\t\t/*Clear the unused FD fields before sending*/\n+\t\t\tmemset(&fd_arr[loop], 0, sizeof(struct qbman_fd));\n+\t\t\tmb_pool = (*ops)->sym->m_src->pool;\n+\t\t\tbpid = mempool_to_bpid(mb_pool);\n+\t\t\tret = build_sec_fd(*ops, &fd_arr[loop], bpid);\n+\t\t\tif (ret) {\n+\t\t\t\tDPAA2_SEC_ERR(\"error: Improper packet contents\"\n+\t\t\t\t\t \" for crypto operation\");\n+\t\t\t\tgoto skip_tx;\n+\t\t\t}\n+\t\t\tops++;\n+\t\t}\n+\n+\t\tloop = 0;\n+\t\tretry_count = 0;\n+\t\twhile (loop < frames_to_send) {\n+\t\t\tret = qbman_swp_enqueue_multiple_desc(swp,\n+\t\t\t\t\t&eqdesc[loop], &fd_arr[loop],\n+\t\t\t\t\tframes_to_send - loop);\n+\t\t\tif (unlikely(ret < 0)) {\n+\t\t\t\tretry_count++;\n+\t\t\t\tif (retry_count > DPAA2_MAX_TX_RETRY_COUNT) {\n+\t\t\t\t\tnum_tx += loop;\n+\t\t\t\t\tnb_ops -= loop;\n+\t\t\t\t\tgoto skip_tx;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tloop += ret;\n+\t\t\t\tretry_count = 0;\n+\t\t\t}\n+\t\t}\n+\n+\t\tnum_tx += loop;\n+\t\tnb_ops -= loop;\n+\t}\n+\n+skip_tx:\n+\tdpaa2_qp->tx_vq.tx_pkts += num_tx;\n+\tdpaa2_qp->tx_vq.err_pkts += nb_ops;\n+\treturn num_tx;\n+}\n+\n static uint16_t\n dpaa2_sec_dequeue_burst(void *qp, struct rte_crypto_op **ops,\n \t\t\tuint16_t nb_ops)\n@@ -3527,6 +3690,10 @@ dpaa2_sec_dev_start(struct rte_cryptodev *dev)\n \n \tPMD_INIT_FUNC_TRACE();\n \n+\t/* Change the tx burst function if ordered queues are used */\n+\tif (priv->en_ordered)\n+\t\tdev->enqueue_burst = dpaa2_sec_enqueue_burst_ordered;\n+\n \tmemset(&attr, 0, sizeof(struct dpseci_attr));\n \n \tret = dpseci_enable(dpseci, CMD_PRI_LOW, priv->token);\n@@ -3739,12 +3906,46 @@ dpaa2_sec_process_atomic_event(struct qbman_swp *swp __rte_unused,\n \n \tev->event_ptr = sec_fd_to_mbuf(fd);\n \tdqrr_index = qbman_get_dqrr_idx(dq);\n-\t*dpaa2_seqn(crypto_op->sym->m_src) = dqrr_index + 1;\n+\t*dpaa2_seqn(crypto_op->sym->m_src) = QBMAN_ENQUEUE_FLAG_DCA | dqrr_index;\n \tDPAA2_PER_LCORE_DQRR_SIZE++;\n \tDPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;\n \tDPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = crypto_op->sym->m_src;\n }\n \n+static void __attribute__((hot))\n+dpaa2_sec_process_ordered_event(struct qbman_swp *swp,\n+\t\t\t\tconst struct qbman_fd *fd,\n+\t\t\t\tconst struct qbman_result *dq,\n+\t\t\t\tstruct dpaa2_queue *rxq,\n+\t\t\t\tstruct rte_event *ev)\n+{\n+\tstruct rte_crypto_op *crypto_op = (struct rte_crypto_op *)ev->event_ptr;\n+\n+\t/* Prefetching mbuf */\n+\trte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-\n+\t\trte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size));\n+\n+\t/* Prefetching ipsec crypto_op stored in priv data of mbuf */\n+\trte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd)-64));\n+\n+\tev->flow_id = rxq->ev.flow_id;\n+\tev->sub_event_type = rxq->ev.sub_event_type;\n+\tev->event_type = RTE_EVENT_TYPE_CRYPTODEV;\n+\tev->op = RTE_EVENT_OP_NEW;\n+\tev->sched_type = rxq->ev.sched_type;\n+\tev->queue_id = rxq->ev.queue_id;\n+\tev->priority = rxq->ev.priority;\n+\tev->event_ptr = sec_fd_to_mbuf(fd);\n+\n+\t*dpaa2_seqn(crypto_op->sym->m_src) = DPAA2_ENQUEUE_FLAG_ORP;\n+\t*dpaa2_seqn(crypto_op->sym->m_src) |= qbman_result_DQ_odpid(dq) <<\n+\t\tDPAA2_EQCR_OPRID_SHIFT;\n+\t*dpaa2_seqn(crypto_op->sym->m_src) |= qbman_result_DQ_seqnum(dq) <<\n+\t\tDPAA2_EQCR_SEQNUM_SHIFT;\n+\n+\tqbman_swp_dqrr_consume(swp, dq);\n+}\n+\n int\n dpaa2_sec_eventq_attach(const struct rte_cryptodev *dev,\n \t\tint qp_id,\n@@ -3762,6 +3963,8 @@ dpaa2_sec_eventq_attach(const struct rte_cryptodev *dev,\n \t\tqp->rx_vq.cb = dpaa2_sec_process_parallel_event;\n \telse if (event->sched_type == RTE_SCHED_TYPE_ATOMIC)\n \t\tqp->rx_vq.cb = dpaa2_sec_process_atomic_event;\n+\telse if (event->sched_type == RTE_SCHED_TYPE_ORDERED)\n+\t\tqp->rx_vq.cb = dpaa2_sec_process_ordered_event;\n \telse\n \t\treturn -EINVAL;\n \n@@ -3780,6 +3983,40 @@ dpaa2_sec_eventq_attach(const struct rte_cryptodev *dev,\n \t\tcfg.options |= DPSECI_QUEUE_OPT_ORDER_PRESERVATION;\n \t\tcfg.order_preservation_en = 1;\n \t}\n+\n+\tif (event->sched_type == RTE_SCHED_TYPE_ORDERED) {\n+\t\tstruct opr_cfg ocfg;\n+\n+\t\t/* Restoration window size = 256 frames */\n+\t\tocfg.oprrws = 3;\n+\t\t/* Restoration window size = 512 frames for LX2 */\n+\t\tif (dpaa2_svr_family == SVR_LX2160A)\n+\t\t\tocfg.oprrws = 4;\n+\t\t/* Auto advance NESN window enabled */\n+\t\tocfg.oa = 1;\n+\t\t/* Late arrival window size disabled */\n+\t\tocfg.olws = 0;\n+\t\t/* ORL resource exhaustaion advance NESN disabled */\n+\t\tocfg.oeane = 0;\n+\t\t/* Loose ordering enabled */\n+\t\tocfg.oloe = 1;\n+\t\tpriv->en_loose_ordered = 1;\n+\t\t/* Strict ordering enabled if explicitly set */\n+\t\tif (getenv(\"DPAA2_STRICT_ORDERING_ENABLE\")) {\n+\t\t\tocfg.oloe = 0;\n+\t\t\tpriv->en_loose_ordered = 0;\n+\t\t}\n+\n+\t\tret = dpseci_set_opr(dpseci, CMD_PRI_LOW, priv->token,\n+\t\t\t\t qp_id, OPR_OPT_CREATE, &ocfg);\n+\t\tif (ret) {\n+\t\t\tRTE_LOG(ERR, PMD, \"Error setting opr: ret: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tqp->tx_vq.cb_eqresp_free = dpaa2_sec_free_eqresp_buf;\n+\t\tpriv->en_ordered = 1;\n+\t}\n+\n \tret = dpseci_set_rx_queue(dpseci, CMD_PRI_LOW, priv->token,\n \t\t\t\t qp_id, &cfg);\n \tif (ret) {\ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\nindex 05bd7c0736..1756d917dd 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\n@@ -1,8 +1,6 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- *\n- * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.\n- * Copyright 2016,2020-2021 NXP\n- *\n+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.\n+ * Copyright 2016,2019-2021 NXP\n */\n \n #ifndef _DPAA2_SEC_PMD_PRIVATE_H_\n@@ -37,6 +35,8 @@ struct dpaa2_sec_dev_private {\n \tuint16_t token; /**< Token required by DPxxx objects */\n \tunsigned int max_nb_queue_pairs;\n \t/**< Max number of queue pairs supported by device */\n+\tuint8_t en_ordered;\n+\tuint8_t en_loose_ordered;\n };\n \n struct dpaa2_sec_qp {\ndiff --git a/drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h b/drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h\nindex 279e8f4d4a..c295c04f24 100644\n--- a/drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h\n+++ b/drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h\n@@ -1,7 +1,7 @@\n /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)\n *\n * Copyright 2013-2016 Freescale Semiconductor Inc.\n- * Copyright 2016-2017 NXP\n+ * Copyright 2016-2020 NXP\n *\n */\n #ifndef __FSL_DPSECI_H\n@@ -11,6 +11,8 @@\n * Contains initialization APIs and runtime control APIs for DPSECI\n */\n \n+#include <fsl_dpopr.h>\n+\n struct fsl_mc_io;\n \n /**\n@@ -41,6 +43,16 @@ int dpseci_close(struct fsl_mc_io *mc_io,\n */\n #define DPSECI_OPT_HAS_CG\t\t\t\t0x000020\n \n+/**\n+ * Enable the Order Restoration support\n+ */\n+#define DPSECI_OPT_HAS_OPR\t\t\t\t0x000040\n+\n+/**\n+ * Order Point Records are shared for the entire DPSECI\n+ */\n+#define DPSECI_OPT_OPR_SHARED\t\t\t\t0x000080\n+\n /**\n * struct dpseci_cfg - Structure representing DPSECI configuration\n * @options: Any combination of the following options:\n", "prefixes": [ "3/8" ] }