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GET /api/patches/105190/?format=api
{ "id": 105190, "url": "http://patches.dpdk.org/api/patches/105190/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1639676975-1316-27-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1639676975-1316-27-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1639676975-1316-27-git-send-email-anoobj@marvell.com", "date": "2021-12-16T17:49:32", "name": "[v2,26/29] crypto/cnxk: add aes cmac", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c22efa03dca8989c855502362840cb7af166e6a2", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1639676975-1316-27-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 20957, "url": "http://patches.dpdk.org/api/series/20957/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20957", "date": "2021-12-16T17:49:06", "name": "New features and improvements in cnxk crypto PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/20957/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105190/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/105190/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 43A9CA0032;\n\tThu, 16 Dec 2021 18:55:23 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B133B4114B;\n\tThu, 16 Dec 2021 18:54:58 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id EE31D4114B\n for <dev@dpdk.org>; Thu, 16 Dec 2021 18:54:56 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1BGBddw6030176\n for <dev@dpdk.org>; Thu, 16 Dec 2021 09:54:56 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3d04s71p9s-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 16 Dec 2021 09:54:56 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 16 Dec 2021 09:54:54 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 16 Dec 2021 09:54:54 -0800", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id 535543F7048;\n Thu, 16 Dec 2021 09:54:52 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=BzIvzfKNZsJHkujVIrPwKrUh46z+w5r25RHzSyzdUao=;\n b=H8vHfQ/PU3hLvn0+N4DfY3dGKvTES9ukdm12PJ31kCQ3RtjpWs1YHJZ2axUHHxnRZBIz\n 7D/K1Z5GFUpz6WjR44+iFxwDzIYLAq52831FE3n+hqWYeueM1eo2x+ef29pPcDxMleJG\n cV+VElxgEn6Kssm6vLVnyZoe/hJFQG+nxkeAjDuBCg3aTUBfswXAI7oQTFgDKn9wsHwp\n C+PKPPZThX5y3Vwq00hOLHN+njO/seZ6yWU1pRZTA30Lu5XllpSlrI1SMGYNq7kN9c28\n LNBJXrCR4SCG/9fat1mLBEyXuwqx5kaICRaWUPkjFuKKf+W4uLgZGnypBwHhMQWXGr0B vw==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Jerin Jacob <jerinj@marvell.com>", "CC": "Anoob Joseph <anoobj@marvell.com>, Archana Muniganti\n <marchana@marvell.com>,\n Tejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH v2 26/29] crypto/cnxk: add aes cmac", "Date": "Thu, 16 Dec 2021 23:19:32 +0530", "Message-ID": "<1639676975-1316-27-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1639676975-1316-1-git-send-email-anoobj@marvell.com>", "References": "<1638859858-734-1-git-send-email-anoobj@marvell.com>\n <1639676975-1316-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "4EgA2MQutE8NmfGjskeyvI9PsffRHraU", "X-Proofpoint-ORIG-GUID": "4EgA2MQutE8NmfGjskeyvI9PsffRHraU", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-16_06,2021-12-16_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for AES CMAC auth algorithm.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\n---\n doc/guides/cryptodevs/cnxk.rst | 1 +\n doc/guides/cryptodevs/features/cn10k.ini | 37 +++++++-------\n doc/guides/cryptodevs/features/cn9k.ini | 37 +++++++-------\n doc/guides/rel_notes/release_22_03.rst | 1 +\n drivers/common/cnxk/roc_se.h | 8 +--\n drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c | 20 ++++++++\n drivers/crypto/cnxk/cnxk_se.h | 60 ++++++++++++++---------\n 7 files changed, 103 insertions(+), 61 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/cnxk.rst b/doc/guides/cryptodevs/cnxk.rst\nindex 6e844f5..3c58517 100644\n--- a/doc/guides/cryptodevs/cnxk.rst\n+++ b/doc/guides/cryptodevs/cnxk.rst\n@@ -61,6 +61,7 @@ Hash algorithms:\n * ``RTE_CRYPTO_AUTH_SHA512_HMAC``\n * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``\n * ``RTE_CRYPTO_AUTH_ZUC_EIA3``\n+* ``RTE_CRYPTO_AUTH_AES_CMAC``\n \n AEAD algorithms:\n \ndiff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini\nindex ab21d9d..c8193c2 100644\n--- a/doc/guides/cryptodevs/features/cn10k.ini\n+++ b/doc/guides/cryptodevs/features/cn10k.ini\n@@ -41,23 +41,26 @@ ZUC EEA3 = Y\n ; Supported authentication algorithms of 'cn10k' crypto driver.\n ;\n [Auth]\n-NULL = Y\n-AES GMAC = Y\n-KASUMI F9 = Y\n-MD5 = Y\n-MD5 HMAC = Y\n-SHA1 = Y\n-SHA1 HMAC = Y\n-SHA224 = Y\n-SHA224 HMAC = Y\n-SHA256 = Y\n-SHA256 HMAC = Y\n-SHA384 = Y\n-SHA384 HMAC = Y\n-SHA512 = Y\n-SHA512 HMAC = Y\n-SNOW3G UIA2 = Y\n-ZUC EIA3 = Y\n+NULL = Y\n+AES GMAC = Y\n+KASUMI F9 = Y\n+MD5 = Y\n+MD5 HMAC = Y\n+SHA1 = Y\n+SHA1 HMAC = Y\n+SHA224 = Y\n+SHA224 HMAC = Y\n+SHA256 = Y\n+SHA256 HMAC = Y\n+SHA384 = Y\n+SHA384 HMAC = Y\n+SHA512 = Y\n+SHA512 HMAC = Y\n+SNOW3G UIA2 = Y\n+ZUC EIA3 = Y\n+AES CMAC (128) = Y\n+AES CMAC (192) = Y\n+AES CMAC (256) = Y\n \n ;\n ; Supported AEAD algorithms of 'cn10k' crypto driver.\ndiff --git a/doc/guides/cryptodevs/features/cn9k.ini b/doc/guides/cryptodevs/features/cn9k.ini\nindex d834659..f215ee0 100644\n--- a/doc/guides/cryptodevs/features/cn9k.ini\n+++ b/doc/guides/cryptodevs/features/cn9k.ini\n@@ -40,23 +40,26 @@ ZUC EEA3 = Y\n ; Supported authentication algorithms of 'cn9k' crypto driver.\n ;\n [Auth]\n-NULL = Y\n-AES GMAC = Y\n-KASUMI F9 = Y\n-MD5 = Y\n-MD5 HMAC = Y\n-SHA1 = Y\n-SHA1 HMAC = Y\n-SHA224 = Y\n-SHA224 HMAC = Y\n-SHA256 = Y\n-SHA256 HMAC = Y\n-SHA384 = Y\n-SHA384 HMAC = Y\n-SHA512 = Y\n-SHA512 HMAC = Y\n-SNOW3G UIA2 = Y\n-ZUC EIA3 = Y\n+NULL = Y\n+AES GMAC = Y\n+KASUMI F9 = Y\n+MD5 = Y\n+MD5 HMAC = Y\n+SHA1 = Y\n+SHA1 HMAC = Y\n+SHA224 = Y\n+SHA224 HMAC = Y\n+SHA256 = Y\n+SHA256 HMAC = Y\n+SHA384 = Y\n+SHA384 HMAC = Y\n+SHA512 = Y\n+SHA512 HMAC = Y\n+SNOW3G UIA2 = Y\n+ZUC EIA3 = Y\n+AES CMAC (128) = Y\n+AES CMAC (192) = Y\n+AES CMAC (256) = Y\n \n ;\n ; Supported AEAD algorithms of 'cn9k' crypto driver.\ndiff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst\nindex e8fec00..72e758e 100644\n--- a/doc/guides/rel_notes/release_22_03.rst\n+++ b/doc/guides/rel_notes/release_22_03.rst\n@@ -63,6 +63,7 @@ New Features\n * Added AES-CTR support in lookaside protocol (IPsec) for CN9K & CN10K.\n * Added NULL cipher support in lookaside protocol (IPsec) for CN9K & CN10K.\n * Added AES-XCBC support in lookaside protocol (IPsec) for CN9K & CN10K.\n+ * Added AES-CMAC support in CN9K & CN10K.\n \n \n Removed Items\ndiff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h\nindex 253575a..145a182 100644\n--- a/drivers/common/cnxk/roc_se.h\n+++ b/drivers/common/cnxk/roc_se.h\n@@ -11,10 +11,10 @@\n #define ROC_SE_FC_MINOR_OP_DECRYPT 0x1\n #define ROC_SE_FC_MINOR_OP_HMAC_FIRST 0x10\n \n-#define ROC_SE_MAJOR_OP_HASH\t 0x34\n-#define ROC_SE_MAJOR_OP_HMAC\t 0x35\n-#define ROC_SE_MAJOR_OP_ZUC_SNOW3G 0x37\n-#define ROC_SE_MAJOR_OP_KASUMI\t 0x38\n+#define ROC_SE_MAJOR_OP_HASH 0x34\n+#define ROC_SE_MAJOR_OP_HMAC 0x35\n+#define ROC_SE_MAJOR_OP_PDCP 0x37\n+#define ROC_SE_MAJOR_OP_KASUMI 0x38\n \n #define ROC_SE_MAJOR_OP_MISC\t\t 0x01\n #define ROC_SE_MISC_MINOR_OP_PASSTHROUGH 0x03\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\nindex 69ee0d9..457e166 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c\n@@ -568,6 +568,26 @@ static const struct rte_cryptodev_capabilities caps_aes[] = {\n \t\t\t}, }\n \t\t}, }\n \t},\n+\t{\t/* AES CMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_AES_CMAC,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 32,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 4,\n+\t\t\t\t\t.max = 4,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n };\n \n static const struct rte_cryptodev_capabilities caps_kasumi[] = {\ndiff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h\nindex a8cd2c5..e988d57 100644\n--- a/drivers/crypto/cnxk/cnxk_se.h\n+++ b/drivers/crypto/cnxk/cnxk_se.h\n@@ -73,11 +73,15 @@ pdcp_iv_copy(uint8_t *iv_d, uint8_t *iv_s, const uint8_t pdcp_alg_type,\n \t\tfor (j = 0; j < 4; j++)\n \t\t\tiv_temp[j] = iv_s_temp[3 - j];\n \t\tmemcpy(iv_d, iv_temp, 16);\n-\t} else {\n+\t} else if (pdcp_alg_type == ROC_SE_PDCP_ALG_TYPE_ZUC) {\n \t\t/* ZUC doesn't need a swap */\n \t\tmemcpy(iv_d, iv_s, 16);\n \t\tif (pack_iv)\n \t\t\tcpt_pack_iv(iv_s, iv_d);\n+\t} else {\n+\t\t/* AES-CMAC EIA2, microcode expects 16B zeroized IV */\n+\t\tfor (j = 0; j < 4; j++)\n+\t\t\tiv_d[j] = 0;\n \t}\n }\n \n@@ -992,8 +996,8 @@ cpt_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n }\n \n static __rte_always_inline int\n-cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n-\t\t struct roc_se_fc_params *params, struct cpt_inst_s *inst)\n+cpt_pdcp_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n+\t\t struct roc_se_fc_params *params, struct cpt_inst_s *inst)\n {\n \tuint32_t size;\n \tint32_t inputlen, outputlen;\n@@ -1014,33 +1018,43 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n \tmac_len = se_ctx->mac_len;\n \tpdcp_alg_type = se_ctx->pdcp_alg_type;\n \n-\tcpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_ZUC_SNOW3G;\n-\n+\tcpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_PDCP;\n \tcpt_inst_w4.s.opcode_minor = se_ctx->template_w4.s.opcode_minor;\n \n \tif (flags == 0x1) {\n \t\tiv_s = params->auth_iv_buf;\n-\t\tiv_len = params->auth_iv_len;\n-\n-\t\tif (iv_len == 25) {\n-\t\t\tiv_len -= 2;\n-\t\t\tpack_iv = 1;\n-\t\t}\n \n \t\t/*\n \t\t * Microcode expects offsets in bytes\n \t\t * TODO: Rounding off\n \t\t */\n \t\tauth_data_len = ROC_SE_AUTH_DLEN(d_lens);\n-\n-\t\t/* EIA3 or UIA2 */\n \t\tauth_offset = ROC_SE_AUTH_OFFSET(d_offs);\n-\t\tauth_offset = auth_offset / 8;\n \n-\t\t/* consider iv len */\n-\t\tauth_offset += iv_len;\n+\t\tif (se_ctx->pdcp_alg_type != ROC_SE_PDCP_ALG_TYPE_AES_CTR) {\n+\t\t\tiv_len = params->auth_iv_len;\n+\n+\t\t\tif (iv_len == 25) {\n+\t\t\t\tiv_len -= 2;\n+\t\t\t\tpack_iv = 1;\n+\t\t\t}\n+\n+\t\t\tauth_offset = auth_offset / 8;\n+\n+\t\t\t/* consider iv len */\n+\t\t\tauth_offset += iv_len;\n+\n+\t\t\tinputlen =\n+\t\t\t\tauth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);\n+\t\t} else {\n+\t\t\tiv_len = 16;\n+\n+\t\t\t/* consider iv len */\n+\t\t\tauth_offset += iv_len;\n+\n+\t\t\tinputlen = auth_offset + auth_data_len;\n+\t\t}\n \n-\t\tinputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);\n \t\toutputlen = mac_len;\n \n \t\toffset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);\n@@ -1056,7 +1070,6 @@ cpt_zuc_snow3g_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n \t\t\tpack_iv = 1;\n \t\t}\n \n-\t\t/* EEA3 or UEA2 */\n \t\t/*\n \t\t * Microcode expects offsets in bytes\n \t\t * TODO: Rounding off\n@@ -1589,8 +1602,7 @@ cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \tif (likely(fc_type == ROC_SE_FC_GEN)) {\n \t\tret = cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, inst);\n \t} else if (fc_type == ROC_SE_PDCP) {\n-\t\tret = cpt_zuc_snow3g_prep(flags, d_offs, d_lens, fc_params,\n-\t\t\t\t\t inst);\n+\t\tret = cpt_pdcp_alg_prep(flags, d_offs, d_lens, fc_params, inst);\n \t} else if (fc_type == ROC_SE_KASUMI) {\n \t\tret = cpt_kasumi_dec_prep(d_offs, d_lens, fc_params, inst);\n \t}\n@@ -1618,8 +1630,7 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \tif (likely(fc_type == ROC_SE_FC_GEN)) {\n \t\tret = cpt_enc_hmac_prep(flags, d_offs, d_lens, fc_params, inst);\n \t} else if (fc_type == ROC_SE_PDCP) {\n-\t\tret = cpt_zuc_snow3g_prep(flags, d_offs, d_lens, fc_params,\n-\t\t\t\t\t inst);\n+\t\tret = cpt_pdcp_alg_prep(flags, d_offs, d_lens, fc_params, inst);\n \t} else if (fc_type == ROC_SE_KASUMI) {\n \t\tret = cpt_kasumi_enc_prep(flags, d_offs, d_lens, fc_params,\n \t\t\t\t\t inst);\n@@ -1883,8 +1894,11 @@ fill_sess_auth(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)\n \t\tauth_type = 0;\n \t\tis_null = 1;\n \t\tbreak;\n-\tcase RTE_CRYPTO_AUTH_AES_XCBC_MAC:\n \tcase RTE_CRYPTO_AUTH_AES_CMAC:\n+\t\tauth_type = ROC_SE_AES_CMAC_EIA2;\n+\t\tzsk_flag = ROC_SE_ZS_IA;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_AES_XCBC_MAC:\n \tcase RTE_CRYPTO_AUTH_AES_CBC_MAC:\n \t\tplt_dp_err(\"Crypto: Unsupported hash algo %u\", a_form->algo);\n \t\treturn -1;\n", "prefixes": [ "v2", "26/29" ] }