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GET /api/patches/105185/?format=api
{ "id": 105185, "url": "http://patches.dpdk.org/api/patches/105185/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1639676975-1316-21-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1639676975-1316-21-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1639676975-1316-21-git-send-email-anoobj@marvell.com", "date": "2021-12-16T17:49:26", "name": "[v2,20/29] crypto/cnxk: use atomics to access CPT res", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "777956795b416991d6c127348705820811b73dd5", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1639676975-1316-21-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 20957, "url": "http://patches.dpdk.org/api/series/20957/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20957", "date": "2021-12-16T17:49:06", "name": "New features and improvements in cnxk crypto PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/20957/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/105185/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/105185/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BB08BA0032;\n\tThu, 16 Dec 2021 18:54:42 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6E9A841160;\n\tThu, 16 Dec 2021 18:54:25 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 9E74241160\n for <dev@dpdk.org>; Thu, 16 Dec 2021 18:54:23 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1BGERCLP008248\n for <dev@dpdk.org>; Thu, 16 Dec 2021 09:54:23 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3d02p0af0y-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 16 Dec 2021 09:54:22 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 16 Dec 2021 09:54:20 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 16 Dec 2021 09:54:20 -0800", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id 4543E3F708A;\n Thu, 16 Dec 2021 09:54:17 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=V6hJs+KwbZAAGxDslVbbjcQKAPHD2gZhGEIrgOOFfBw=;\n b=BSofMKDFsYaupJf93oAS047KYk7SVlra3uxQyJzfvVs8dmhb/+rskuZrbWNEjFLypB8B\n jQVI1T2ZWXwCuu/26XM1n6PlMnzJWf2re/XBdrpj47mjcYzgGTnEbUlJ7TeUJc9aG8yG\n h7MffDEKxJMd9Ngnc9lva1g93h3fv+Qo2IvbD/dJSPDsuh+dNuADQXRAZtQlLxrKdeD/\n BZEgIOUfUegAvXQZa+bIwjIFu+fdN1Xb+ndjEWOr+EJ+XkflUayppTOaHIqhErec+WXL\n Q2nb+FhB+ZNS14kUhky0Wy6Z6abAsyHGEpAI+ZLm+XuQP6p3hTfxvEmd0+ji9Evs6tYI VQ==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Jerin Jacob <jerinj@marvell.com>", "CC": "Anoob Joseph <anoobj@marvell.com>, Archana Muniganti\n <marchana@marvell.com>,\n Tejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH v2 20/29] crypto/cnxk: use atomics to access CPT res", "Date": "Thu, 16 Dec 2021 23:19:26 +0530", "Message-ID": "<1639676975-1316-21-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1639676975-1316-1-git-send-email-anoobj@marvell.com>", "References": "<1638859858-734-1-git-send-email-anoobj@marvell.com>\n <1639676975-1316-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "5Pl2UBtCjvBU-6K4T9RTfgFWubhGcOIc", "X-Proofpoint-ORIG-GUID": "5Pl2UBtCjvBU-6K4T9RTfgFWubhGcOIc", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-16_06,2021-12-16_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The memory would be updated by hardware. Use atomics to read the same.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\n---\n drivers/common/cnxk/hw/cpt.h | 2 ++\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 24 ++++++++++++++++--------\n drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 28 +++++++++++++++++++---------\n 3 files changed, 37 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h\nindex ccc7af4..412dd76 100644\n--- a/drivers/common/cnxk/hw/cpt.h\n+++ b/drivers/common/cnxk/hw/cpt.h\n@@ -215,6 +215,8 @@ union cpt_res_s {\n \n \t\tuint64_t reserved_64_127;\n \t} cn9k;\n+\n+\tuint64_t u64[2];\n };\n \n /* [CN10K, .) */\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex 638268e..f8240e1 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -111,6 +111,10 @@ cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[],\n \tuint64_t w7;\n \tint ret;\n \n+\tconst union cpt_res_s res = {\n+\t\t.cn10k.compcode = CPT_COMP_NOT_DONE,\n+\t};\n+\n \top = ops[0];\n \n \tinst[0].w0.u64 = 0;\n@@ -174,7 +178,7 @@ cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[],\n \t}\n \n \tinst[0].res_addr = (uint64_t)&infl_req->res;\n-\tinfl_req->res.cn10k.compcode = CPT_COMP_NOT_DONE;\n+\t__atomic_store_n(&infl_req->res.u64[0], res.u64[0], __ATOMIC_RELAXED);\n \tinfl_req->cop = op;\n \n \tinst[0].w7.u64 = w7;\n@@ -395,9 +399,9 @@ cn10k_cpt_sec_ucc_process(struct rte_crypto_op *cop,\n static inline void\n cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp,\n \t\t\t struct rte_crypto_op *cop,\n-\t\t\t struct cpt_inflight_req *infl_req)\n+\t\t\t struct cpt_inflight_req *infl_req,\n+\t\t\t struct cpt_cn10k_res_s *res)\n {\n-\tstruct cpt_cn10k_res_s *res = (struct cpt_cn10k_res_s *)&infl_req->res;\n \tconst uint8_t uc_compcode = res->uc_compcode;\n \tconst uint8_t compcode = res->compcode;\n \tunsigned int sz;\n@@ -495,12 +499,15 @@ cn10k_cpt_crypto_adapter_dequeue(uintptr_t get_work1)\n \tstruct cpt_inflight_req *infl_req;\n \tstruct rte_crypto_op *cop;\n \tstruct cnxk_cpt_qp *qp;\n+\tunion cpt_res_s res;\n \n \tinfl_req = (struct cpt_inflight_req *)(get_work1);\n \tcop = infl_req->cop;\n \tqp = infl_req->qp;\n \n-\tcn10k_cpt_dequeue_post_process(qp, infl_req->cop, infl_req);\n+\tres.u64[0] = __atomic_load_n(&infl_req->res.u64[0], __ATOMIC_RELAXED);\n+\n+\tcn10k_cpt_dequeue_post_process(qp, infl_req->cop, infl_req, &res.cn10k);\n \n \tif (unlikely(infl_req->op_flags & CPT_OP_FLAGS_METABUF))\n \t\trte_mempool_put(qp->meta_info.pool, infl_req->mdata);\n@@ -515,9 +522,9 @@ cn10k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \tstruct cpt_inflight_req *infl_req;\n \tstruct cnxk_cpt_qp *qp = qptr;\n \tstruct pending_queue *pend_q;\n-\tstruct cpt_cn10k_res_s *res;\n \tuint64_t infl_cnt, pq_tail;\n \tstruct rte_crypto_op *cop;\n+\tunion cpt_res_s res;\n \tint i;\n \n \tpend_q = &qp->pend_q;\n@@ -534,9 +541,10 @@ cn10k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \tfor (i = 0; i < nb_ops; i++) {\n \t\tinfl_req = &pend_q->req_queue[pq_tail];\n \n-\t\tres = (struct cpt_cn10k_res_s *)&infl_req->res;\n+\t\tres.u64[0] = __atomic_load_n(&infl_req->res.u64[0],\n+\t\t\t\t\t __ATOMIC_RELAXED);\n \n-\t\tif (unlikely(res->compcode == CPT_COMP_NOT_DONE)) {\n+\t\tif (unlikely(res.cn10k.compcode == CPT_COMP_NOT_DONE)) {\n \t\t\tif (unlikely(rte_get_timer_cycles() >\n \t\t\t\t pend_q->time_out)) {\n \t\t\t\tplt_err(\"Request timed out\");\n@@ -553,7 +561,7 @@ cn10k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \n \t\tops[i] = cop;\n \n-\t\tcn10k_cpt_dequeue_post_process(qp, cop, infl_req);\n+\t\tcn10k_cpt_dequeue_post_process(qp, cop, infl_req, &res.cn10k);\n \n \t\tif (unlikely(infl_req->op_flags & CPT_OP_FLAGS_METABUF))\n \t\t\trte_mempool_put(qp->meta_info.pool, infl_req->mdata);\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\nindex 449208d..cf80d47 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n@@ -221,6 +221,10 @@ cn9k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \tuint64_t head;\n \tint ret;\n \n+\tconst union cpt_res_s res = {\n+\t\t.cn10k.compcode = CPT_COMP_NOT_DONE,\n+\t};\n+\n \tpend_q = &qp->pend_q;\n \n \tconst uint64_t lmt_base = qp->lf.lmt_base;\n@@ -274,10 +278,12 @@ cn9k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \t\tinfl_req_1->op_flags = 0;\n \t\tinfl_req_2->op_flags = 0;\n \n-\t\tinfl_req_1->res.cn9k.compcode = CPT_COMP_NOT_DONE;\n+\t\t__atomic_store_n(&infl_req_1->res.u64[0], res.u64[0],\n+\t\t\t\t __ATOMIC_RELAXED);\n \t\tinst[0].res_addr = (uint64_t)&infl_req_1->res;\n \n-\t\tinfl_req_2->res.cn9k.compcode = CPT_COMP_NOT_DONE;\n+\t\t__atomic_store_n(&infl_req_2->res.u64[0], res.u64[0],\n+\t\t\t\t __ATOMIC_RELAXED);\n \t\tinst[1].res_addr = (uint64_t)&infl_req_2->res;\n \n \t\tret = cn9k_cpt_inst_prep(qp, op_1, infl_req_1, &inst[0]);\n@@ -410,9 +416,9 @@ cn9k_cpt_sec_post_process(struct rte_crypto_op *cop,\n \n static inline void\n cn9k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, struct rte_crypto_op *cop,\n-\t\t\t struct cpt_inflight_req *infl_req)\n+\t\t\t struct cpt_inflight_req *infl_req,\n+\t\t\t struct cpt_cn9k_res_s *res)\n {\n-\tstruct cpt_cn9k_res_s *res = (struct cpt_cn9k_res_s *)&infl_req->res;\n \tunsigned int sz;\n \n \tif (likely(res->compcode == CPT_COMP_GOOD)) {\n@@ -492,12 +498,15 @@ cn9k_cpt_crypto_adapter_dequeue(uintptr_t get_work1)\n \tstruct cpt_inflight_req *infl_req;\n \tstruct rte_crypto_op *cop;\n \tstruct cnxk_cpt_qp *qp;\n+\tunion cpt_res_s res;\n \n \tinfl_req = (struct cpt_inflight_req *)(get_work1);\n \tcop = infl_req->cop;\n \tqp = infl_req->qp;\n \n-\tcn9k_cpt_dequeue_post_process(qp, infl_req->cop, infl_req);\n+\tres.u64[0] = __atomic_load_n(&infl_req->res.u64[0], __ATOMIC_RELAXED);\n+\n+\tcn9k_cpt_dequeue_post_process(qp, infl_req->cop, infl_req, &res.cn9k);\n \n \tif (unlikely(infl_req->op_flags & CPT_OP_FLAGS_METABUF))\n \t\trte_mempool_put(qp->meta_info.pool, infl_req->mdata);\n@@ -512,9 +521,9 @@ cn9k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \tstruct cpt_inflight_req *infl_req;\n \tstruct cnxk_cpt_qp *qp = qptr;\n \tstruct pending_queue *pend_q;\n-\tstruct cpt_cn9k_res_s *res;\n \tuint64_t infl_cnt, pq_tail;\n \tstruct rte_crypto_op *cop;\n+\tunion cpt_res_s res;\n \tint i;\n \n \tpend_q = &qp->pend_q;\n@@ -531,9 +540,10 @@ cn9k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \tfor (i = 0; i < nb_ops; i++) {\n \t\tinfl_req = &pend_q->req_queue[pq_tail];\n \n-\t\tres = (struct cpt_cn9k_res_s *)&infl_req->res;\n+\t\tres.u64[0] = __atomic_load_n(&infl_req->res.u64[0],\n+\t\t\t\t\t __ATOMIC_RELAXED);\n \n-\t\tif (unlikely(res->compcode == CPT_COMP_NOT_DONE)) {\n+\t\tif (unlikely(res.cn9k.compcode == CPT_COMP_NOT_DONE)) {\n \t\t\tif (unlikely(rte_get_timer_cycles() >\n \t\t\t\t pend_q->time_out)) {\n \t\t\t\tplt_err(\"Request timed out\");\n@@ -550,7 +560,7 @@ cn9k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \n \t\tops[i] = cop;\n \n-\t\tcn9k_cpt_dequeue_post_process(qp, cop, infl_req);\n+\t\tcn9k_cpt_dequeue_post_process(qp, cop, infl_req, &res.cn9k);\n \n \t\tif (unlikely(infl_req->op_flags & CPT_OP_FLAGS_METABUF))\n \t\t\trte_mempool_put(qp->meta_info.pool, infl_req->mdata);\n", "prefixes": [ "v2", "20/29" ] }